Reconstituted wafer stack packaging with after-applied pad extensions

• US 8,461,672 B2
• Filed: 07/25/2008
• Issued: 06/11/2013
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Humpston, Giles, Ovrutsky, David, Mirkarimi, Laura
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US12/670,952
• Publication Number:
  US 20110006432A1
• Time in Patent Office: 1,782 Days
• Field of Search: 257/E21.499, 257/E23.169, 257/E23.019, 257/E23.142, 257/E23.178, 257/E23.085, 257/94, 257/95, 257/99, 257/103, 257/685, 257/686, 257/758, 257/773, 257/777, 257/781, 257/786, 438/107, 438/109, 438/110, 438/113, 438/462
• US Class Current: 257/686
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements (12, 12A) each having a front surface (117), contacts (22) exposed at the front surface, a rear surface (118) and edges (18, 20) extending between the front and rear surfaces. Traces (24) connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face (90) of the microelectronic unit. A plurality of conductors (66) may extend along edges of the microelectronic elements from the traces (24) to the top face (90). The conductors may be conductively connected with unit contacts (76) such that the unit contacts overlie the rear surface (118) of the at least one microelectronic element (12A) adjacent to the top face.

Claims

1. A method of fabricating a plurality of stacked microelectronic units, comprising:

a) providing a plurality of subassemblies each being a reconstituted wafer or portion of a reconstituted wafer and each having a front side and a rear side remote from the front side, each subassembly including a plurality of spaced apart microelectronic elements each including a semiconductor chip, the microelectronic elements having front faces exposed at the front side, contacts exposed at the front side, rear faces adjacent to the rear side, and edges extending between the front and rear faces, each subassembly further including a fill layer overlying the rear faces of the microelectronic elements and extending between the edges of adjacent microelectronic elements;

b) forming a plurality of traces at the front side of each subassembly, the traces extending from the contacts to beyond the edges of the microelectronic elements;

c) reducing a thickness of a first one of the subassemblies from the rear side to reduce a thickness of the microelectronic elements therein;

d) joining a second one of the subassemblies with the first subassembly such that the front side of the second subassembly confronts the rear side of the first subassembly and such that the front faces of microelectronic elements of the second subassembly confront the rear faces of the microelectronic elements of the first subassembly;

e) forming leads in at least one opening extending downwardly from the rear side of the second subassembly, the leads connected to the traces of the microelectronic elements of the first and second subassemblies, the at least one opening having an inclined wall at an angle relative to a normal direction with respect to the plane defined by the front faces of the microelectronic elements; and

f) severing the joined microelectronic assemblies along edges of the microelectronic elements into stacked microelectronic units, such that edge surfaces of the microelectronic units include an inclined wall of the at least one opening, each microelectronic unit including leads extending along the surface of the at least one inclined wall.

2. A method as claimed in claim 1, wherein the microelectronic elements of the first subassembly are thinned until each microelectronic element therein reaches a thickness of less than about 50 microns between the front face and the rear face.

3. A method as claimed in claim 2, wherein the microelectronic elements of the first subassembly are thinned until each microelectronic element therein reaches a thickness of about 15 microns or less between the front face and the rear face.

4. A method as claimed in claim 1, wherein at least one of the microelectronic elements includes flash memory.

5. A method as claimed in claim 4, wherein each of the microelectronic elements includes flash memory.

6. A method as claimed in claim 1, wherein the traces extend along a passivation layer having openings aligned with the contacts.

7. A method as claimed in claim 1, further comprising thinning the second subassembly from the rear side to reduce a thickness of the microelectronic elements therein prior to forming the leads.

8. A method as claimed in claim 7, further comprising joining a third one of the subassemblies with the second subassembly such that the front side of the third subassembly confronts the rear side of the second subassembly, wherein step (e) includes forming leads connected to the traces of the microelectronic elements of the third subassembly.

9. A method as claimed in claim 8, further comprising grinding the third subassembly from the rear side thereof to reduce a thickness of the microelectronic elements therein and joining a fourth one of the subassemblies with the third subassembly such that the front side of the fourth subassembly confronts the rear side of the third subassembly, wherein step (e) includes forming leads connected to the traces of the microelectronic elements of the fourth subassembly.

10. A method as claimed in claim 7, wherein, prior to the step of grinding the second subassembly the thickness of the microelectronic elements of the second subassembly is substantially the same as a thickness of a wafer from which the microelectronic elements therein are obtained, prior to their incorporation in the second subassembly.

11. A method as claimed in claim 1, wherein step (e) includes forming the at least one opening as a plurality of channels extending in a lateral direction aligned with the plane defined by the front faces and along adjacent edges of the microelectronic elements.

12. A method as claimed in claim 11, wherein at least some of the leads extend in parallel paths spaced apart in the lateral direction along the inclined wall of one of the channels.

13. A method as claimed in claim 1, wherein step (e) includes forming a plurality of spaced apart openings in a lateral direction extending along edges of adjacent ones of the microelectronic elements and forming the leads in the spaced apart openings, each lead connected to a single one of the contacts.

14. A method as claimed in claim 1, wherein, at least prior to step (c), the fill layer covers the rear faces of the microelectronic elements.

15. A method as claimed in claim 1, further comprising, prior to step (c), attaching an element to the front side of the first subassembly.

16. A method as claimed in claim 15, wherein the element includes a packaging layer.

17. A method as claimed in claim 16, wherein the packaging layer electrically isolates the contacts from the front side of the first subassembly.

18. A method as claimed in claim 1, wherein, prior to step ,(b) the thickness of the microelectronic elements of the first subassembly is substantially the same as a thickness of a wafer from which the microelectronic elements therein are obtained, prior to their incorporation in the first subassembly.

19. A method of fabricating a plurality of stacked microelectronic units, comprising:

a) providing a plurality of subassemblies each being a reconstituted wafer or portion of a reconstituted wafer and each having a front side and a rear side remote from the front side, each subassembly including a plurality of spaced apart microelectronic elements each including a semiconductor chip, the microelectronic elements having front faces exposed at the front side, contacts exposed at the front side, rear faces adjacent to the rear side, and edges extending between the front and rear faces, each subassembly further including a plurality of traces extending from the contacts to beyond the edges of the microelectronic elements and a fill layer overlying the rear faces of the microelectronic elements and extending between the edges of adjacent microelectronic elements;

b) reducing a thickness of a first one of the subassemblies from the rear side so as to reduce a thickness of the microelectronic elements therein;

c) joining a second one of the subassemblies with the first subassembly such that the front faces of the microelectronic elements of the second subassembly overlie and confront the rear faces of the microelectronic elements of the first subassembly;

d) forming leads in at least one opening extending downwardly from the rear side of the second subassembly, the leads being conductively connected to the traces of the microelectronic elements of the first and second subassemblies, the at least one opening having an inclined wall at an angle relative to a normal direction with respect to the plane defined by the front faces of the microelectronic elements; and

e) severing the joined microelectronic assemblies along edges of the microelectronic elements into stacked microelectronic units, such that edge surfaces of the microelectronic units include an inclined wall of the at least one opening, each microelectronic unit including leads extending along the surface of the at least one inclined wall.

20. A method as claimed in claim 19, wherein the fill layer includes a polymer.

21. A method as claimed in claim 19, wherein step (a) includes temporarily joining the front faces of a plurality of individual microelectronic elements to a carrier layer such that the edges of adjacent microelectronic elements are spaced apart by at least a predetermined spacing.

22. A method as claimed in claim 21, wherein step (a) further includes forming the fill layer by flowing an organic material at least into spaces between edges of adjacent joined microelectronic elements.

23. A method as claimed in claim 22, wherein step (a) further includes forming the traces after forming the fill layer.

24. A method as claimed in claim 19, wherein the front faces of the microelectronic elements of the first subassembly have at least one dimension different from a corresponding dimension of the front faces of the microelectronic elements of the second subassembly.

25. A method as claimed in claim 19, wherein a front face of a given microelectronic element of the first subassembly has at least one dimension different from a corresponding dimension of a front face of another microelectronic element of the first subassembly.

26. A method as claimed in claim 25, wherein front faces of a vertically stacked pair of microelectronic elements within the stacked assembly have at least substantially the same dimensions.

27. A method as claimed in claim 19, wherein each subassembly further includes alignment features adjacent to the front side.

28. A method as claimed in claim 27, wherein the alignment features and the traces are elements of a metal layer exposed at the front side.

29. A method as claimed in claim 19, wherein step (d) includes joining the second subassembly to the first subassembly such that edges of microelectronic elements of the second subassembly are displaced in a lateral direction relative to edges of microelectronic elements of the first subassembly in vertical alignment therewith, and the opening formed in step (e) has a sloped wall exposing the traces adjacent to the laterally displaced edges of the vertically stacked microelectronic elements.

30. A method as claimed in claim 29, wherein the lateral direction is a first lateral direction, the edges of each microelectronic element include first edges and second edges transverse to the first edges, and step (d) includes joining the second subassembly to the first subassembly such that second edges of microelectronic elements of the second subassembly are further displaced in a second lateral direction relative to second edges of microelectronic elements of the first subassembly in vertical alignment therewith, the second lateral direction being transverse to the first lateral direction, the method further comprising forming a second opening having a sloped wall exposing second traces adjacent to the second edges, and forming leads connected to the second traces.

31. A method of fabricating a stacked microelectronic unit, comprising:

a) stacking and joining a plurality of microelectronic elements, each of the microelectronic elements having a front face, a rear face remote from the front face, contacts exposed at the front face, edges extending between the front and rear faces and traces connected to the contacts extending along the front face towards the edges, the front faces of at least some of the microelectronic elements overlying and confronting the rear faces of other microelectronic elements; and

b) forming a plurality of conductors extending along the edges of the microelectronic elements from the traces to unit contacts overlying and adjacent to rear faces of microelectronic elements of the at least some microelectronic elements.

32. A method of fabricating a stacked microelectronic unit as claimed in claim 31, wherein each of the plurality of microelectronic elements is included in a microelectronic subassembly containing a plurality of microelectronic elements arranged in an array, wherein step (a) includes stacking and joining a plurality of the microelectronic subassemblies and forming a plurality of openings extending between edges of stacked microelectronic elements therein.

33. A stacked microelectronic unit as claimed in claim 31, further comprising at least some unit contacts exposed at the bottom face, the unit contacts being connected to contacts on a front surface of at least one microelectronic element adjacent to the bottom face.

34. A stacked microelectronic unit, the stacked unit having a top face, unit contacts exposed at the top face and a bottom face remote from the top face, the stacked unit comprising:

a) a plurality of vertically stacked microelectronic elements each having a front surface, a rear surface, contacts exposed at the front surface, edges extending between the front and rear surfaces, traces connected to the contacts extending along the front surfaces towards the edges, the rear surface of at least one of the stacked microelectronic elements being adjacent to the top face of the microelectronic unit;

b) a plurality of conductors extending along the edges of the microelectronic elements from the traces to the top surface, the conductors conductively connected with the unit contacts, such that the unit contacts overlie the rear surface of the at least one microelectronic element adjacent to the top face.

35. A stacked microelectronic unit as claimed in claim 34, wherein the laterally displaced edges are first edges extending in a first direction, the edges of the microelectronic elements including second edges extending in a second direction transverse to the first direction, each of the first and second microelectronic elements having at least one second edge laterally displaced from an adjacent second edge of the other of the first and second microelectronic elements, the dielectric layer overlying the second edges of the microelectronic elements and extending along the second edges of the microelectronic elements to unit contacts.

36. A stacked microelectronic unit, comprising:

first and second vertically stacked microelectronic elements, each having a front surface defining a lateral direction, at least one edge extending away from the front surface, contacts exposed at the front surface, and traces extending from the contacts toward the edges, the front surface of the second microelectronic element at least partially overlying the front surface of the first microelectronic element, the second microelectronic element having at least one edge displaced in the lateral direction from an adjacent edge of the first microelectronic element;

a dielectric layer overlying the laterally displaced edges of the microelectronic elements, the dielectric layer defining an edge of the stacked unit; and

leads connected to traces at front faces of the microelectronic elements, the leads extending along the edges of the microelectronic elements to unit contacts.

37. A stacked microelectronic unit, comprising:

first and second vertically stacked microelectronic elements, wherein at least one first edge of the first microelectronic element at a first level extends beyond a corresponding first edge of the second microelectronic element at a second level overlying the first level;

a dielectric layer overlying the first edges of the first and second microelectronic elements, the dielectric layer defining a first edge of the stacked unit; and

conductive vias extending through the dielectric layer, the vias being connected to traces at front faces of the microelectronic elements.

38. A stacked microelectronic unit, comprising:

first and second vertically stacked microelectronic elements, wherein a front face of the first microelectronic element overlies at least one of a front face or a rear face of the second microelectronic element and at least one of a width or a length of the front faces of the first and second microelectronic elements differing;

a dielectric layer overlying the first edges of the first and second microelectronic elements; and

leads connected to traces at front faces of the microelectronic elements, the leads extending along a first edge of the stacked unit.