Edge connect wafer level stacking

• US 8,461,673 B2
• Filed: 02/09/2012
• Issued: 06/11/2013
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US13/369,846
• Publication Number:
  US 20120133057A1
• Time in Patent Office: 488 Days
• Field of Search: 257/686
• US Class Current: 257/686
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly.

Claims

1. A microelectronic package comprising:

a first microelectronic assembly including a plurality of first semiconductor chips having respective first chip contacts electrically connected with one another, and at least one first conductive element at a face of the first assembly electrically connected with the first chip contacts;

a second microelectronic assembly including a plurality of second semiconductor chips having second chip contacts electrically with one another, and at least one second conductive element at a face of the second assembly electrically connected with the second chip contacts;

a bond wire electrically connecting the at least one first conductive element with the at least one second conductive element; and

wherein at least one of the first assembly or the second assembly includes a package terminal at the face thereof, wherein the package terminal is a bump solderable to a conductive contact of an external component and is electrically connected with the at least one first conductive element and the at least one second conductive element.

2. The microelectronic package as claimed in claim 1, wherein at least one of the first assembly or the second assembly is configured to provide memory storage array function.

3. The microelectronic package as claimed in claim 1, wherein semiconductor chips of the plurality of semiconductor chips in at least one of the first assembly or the second assembly are arranged in a stack.

4. The microelectronic package as claimed in claim 1, further comprising an electrically conductive joining unit joined to the package terminal.

5. The microelectronic package as claimed in claim 1, wherein the bond wire extends about an edge of one of the first assembly and the second assembly.

6. The microelectronic package as claimed in claim 1, wherein at least one of the at least one first or the at least one second conductive elements is a land.

16. The microelectronic package as claimed in claim 1, wherein the external component is a circuit board or circuit panel.

7. A method of fabricating a microelectronic assembly comprising:

stacking a first microelectronic assembly onto a second microelectronic assembly,

the first microelectronic assembly including a plurality of first semiconductor chips having respective first chip contacts electrically connected with one another, and at least one first conductive element at a face of the first assembly electrically connected with the first chip contacts,

the second microelectronic assembly including a plurality of second semiconductor chips having respective second chip contacts electrically connected with one another, and at least one second conductive element at a face of the second assembly electrically connected with the second chip contacts; and

forming a bond wire electrically connecting the at least one first conductive element with the at least one second conductive element, the at least one first and second conductive elements being electrically connected with a package terminal at the face of at least one of the first assembly or the second assembly, the package terminal being a bump solderable to a conductive contact of an external component.

8. The method as claimed in claim 7, wherein at least one of the first assembly or the second assembly is configured to predominantly provide memory storage array function.

9. The method as claimed in claim 7, wherein semiconductor chips of the plurality of semiconductor chips in at least one of the first assembly or the second assembly are arranged in a stack.

10. The method as claimed in claim 7 further comprising:

joining an electrically conductive joining unit to the package terminal.

11. The method as claimed in claim 7, wherein the step of forming the bond wire forms the bond wire to extend about an edge of one of the first assembly and the second assembly.

12. The method as claimed in claim 7, further comprising functionally testing at least one of the first or second microelectronic assemblies prior to the step of stacking.

13. The method as claimed in claim 7, further comprising functionally testing each of the first or second microelectronic assemblies prior to the step of stacking.

14. The method as claimed in claim 7, wherein at least one of the first or second microelectronic assemblies units is of a wafer.

15. The method as claimed in claim 7, wherein at least one of the first or second conductive elements is a land.

17. The method as claimed in claim 7, wherein the external component is a circuit board or circuit panel.

18. A microelectronic assembly comprising:

a microelectronic package and a component external to the microelectronic package,

where the microelectronic package includes;

a first microelectronic assembly including a plurality of first semiconductor chips having respective first chip contacts electrically connected with one another, and at least one first conductive element at a face of the first assembly electrically connected with the first chip contacts;

a second microelectronic assembly including a plurality of second semiconductor chips having second chip contacts electrically with one another, and at least one second conductive element at a face of the second assembly electrically connected with the second chip contacts;

a bond wire electrically connecting the at least one first conductive element with the at least one second conductive element; and

wherein at least one of the first assembly or the second assembly includes a package terminal at the face thereof, wherein the package terminal is soldered to a conductive contact of the external component and is electrically connected with the at least one first conductive element and the at least one second conductive element.

19. A method of fabricating a microelectronic assembly comprising:

stacking a first microelectronic assembly onto a second microelectronic assembly,

the first microelectronic assembly including a plurality of first semiconductor chips having respective first chip contacts electrically connected with one another, and at least one first conductive element at a face of the first assembly electrically connected with the first chip contacts, and

the second microelectronic assembly including a plurality of second semiconductor chips having respective second chip contacts electrically connected with one another, and at least one second conductive element at a face of the second assembly electrically connected with the second chip contacts;

forming a bond wire electrically connecting the at least one first conductive element with the at least one second conductive element, the at least one first and second conductive elements being electrically connected with a package terminal at the face of at least one of the first assembly or the second assembly; and

soldering the package terminal to a conductive contact of the external component, the package terminal being electrically connected with the at least one first conductive element and the at least one second conductive element.