Digital circuits having improved transistors, and methods therefor
First Claim
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1. A circuit, comprising:
- a plurality of transistors having controllable current paths coupled between a first logic node and a second logic node, the transistors configured to selectively couple an output node to the first or second logic node in response to at least one input signal;
the plurality of transistors forming at least one static random access memory (SRAM) cell, each SRAM cell includingat least one latch, andat least one access transistor having a source-drain path coupled between a bit line and the output node;
whereinat least one of the transistors of the SRAM cell has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.
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Abstract
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
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22 Claims
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1. A circuit, comprising:
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a plurality of transistors having controllable current paths coupled between a first logic node and a second logic node, the transistors configured to selectively couple an output node to the first or second logic node in response to at least one input signal; the plurality of transistors forming at least one static random access memory (SRAM) cell, each SRAM cell including at least one latch, and at least one access transistor having a source-drain path coupled between a bit line and the output node;
whereinat least one of the transistors of the SRAM cell has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region. - View Dependent Claims (2, 3, 4, 5, 15, 16, 17, 18, 19)
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6. An integrated circuit device, comprising:
a digital circuit comprising a plurality of deeply depleted channel (DDC) transistors, each having a screening layer fully covering and in contact with a doped body region and positioned under and fully covered by a substantially undoped channel, the screening layer having a doping concentration greater than a body of the at least one transistor, the deeply depleted channel transistors configured to drive an output node between at least two voltage levels in response to at least one input signal that varies between the two voltage levels, the digital circuit includes at least one latch comprising a first driver DDC transistor having a source-drain path coupled between the output node and a first voltage level, and a gate coupled to a complementary node, a second driver DDC transistor having a source-drain path coupled between the complementary node and the first voltage level, and a gate coupled to the output node, and first and second load devices coupled between the output node and complementary node, respectively, and the second voltage level. - View Dependent Claims (7, 8, 9, 10, 20, 21, 22)
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11. A method, comprising:
controlling a current in a digital circuit with at least one deeply depleted channel transistor having a substantially undoped channel region fully formed over a relatively highly doped screening layer fully formed over and in contact with a doped body region, controlling the current including providing matched deeply depleted channel transistors as cross-coupled driver transistors of a latch circuit. - View Dependent Claims (12, 13, 14)
Specification