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Digital circuits having improved transistors, and methods therefor

  • US 8,461,875 B1
  • Filed: 02/18/2011
  • Issued: 06/11/2013
  • Est. Priority Date: 02/18/2011
  • Status: Active Grant
First Claim
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1. A circuit, comprising:

  • a plurality of transistors having controllable current paths coupled between a first logic node and a second logic node, the transistors configured to selectively couple an output node to the first or second logic node in response to at least one input signal;

    the plurality of transistors forming at least one static random access memory (SRAM) cell, each SRAM cell includingat least one latch, andat least one access transistor having a source-drain path coupled between a bit line and the output node;

    whereinat least one of the transistors of the SRAM cell has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.

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