SOI switch enhancement

• US 8,461,903 B1
• Filed: 09/13/2010
• Issued: 06/11/2013
• Est. Priority Date: 09/11/2009
• Status: Expired due to Fees

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Granger-Jones, Marcus
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US12/880,634
• Time in Patent Office: 1,002 Days
• Field of Search: 327/427
• US Class Current: 327/427
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.

Claims

1. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:

a plurality of field effect transistor (FET) devices, where each FET device of the plurality of FET devices includes a gate contact, a drain contact, and a source contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled at a second end of the chain, and wherein the gate contact of the FET device at the second end of the chain is a first gate contact;

a plurality of gate biasing circuits coupled in series, wherein each of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices;

a common biasing circuit having a first terminal and a second terminal, wherein the first terminal is coupled to the first gate contact;

a plurality of drain-source circuits coupled in series, wherein each of the plurality of drain-source circuits is coupled between a corresponding drain contact and source contact of one of the plurality of FET devices; and

a plurality of drain-source speedup circuits, wherein each drain-source speedup circuit of the plurality of drain-source speedup circuits is coupled across a corresponding drain-source circuit of the plurality of drain-source circuits.

2. The serially stacked SOI switch of claim 1, wherein each one of the plurality of drain-source speedup circuits comprises:

a pFET transistor including a drain contact coupled to a first speedup node, a gate contact coupled to a second speedup node, and a source contact coupled to a third speedup node;

an nFET transistor including a drain contact coupled to the first speedup node, a gate contact coupled to the second speedup node, and a source contact coupled to the third speedup node.

3. The serially stacked SOI switch of claim 2, wherein the plurality of drain-source speedup circuits are coupled together in series at the second speedup node of each one of the drain-source speedup circuits by a plurality of switch resistors such that a single switch resistor is coupled between each second speedup node of the plurality of drain-source speedup circuits.

4. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:

a plurality of field effect transistor (FET) devices, where each FET device of the plurality of FET devices includes a gate contact, a drain contact, a source contact, and a body contact and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled at a second end of the chain, and wherein the gate contact and the body contact of the FET device at the second end of the chain are a first gate contact and a first body contact;

a plurality of gate biasing circuits coupled in series, wherein each of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices;

a common biasing circuit having a first terminal and a second terminal, wherein the first terminal is coupled to the first gate contact;

a plurality of drain-source circuits coupled in series, wherein each of the plurality of drain-source circuits is coupled between a corresponding drain contact and source contact of one of the plurality of FET devices;

a plurality of body biasing circuits coupled in series, wherein each of the plurality of body biasing circuits is coupled to the body contact of a corresponding FET device and the body contact of an adjacent FET device;

a common body biasing circuit having a first terminal and a second terminal, wherein the first terminal of the common body biasing circuit is coupled to the first body contact; and

a plurality of body speedup circuits, wherein each body speedup circuit of the plurality of body speedup circuits is coupled across a corresponding one of the plurality of body biasing circuits.

5. The serially stacked SOI switch of claim 4, wherein each one of the plurality of body speedup circuits comprises:

a pFET transistor including a drain contact coupled to a first speedup node, a gate contact coupled to a second speedup node, and a source contact coupled to a third speedup node;

an nFET transistor including a drain contact coupled to the first speedup node, a gate contact coupled to the second speedup node, and a source contact coupled to the third speedup node.

6. The serially stacked SOI switch of claim 5, wherein the plurality of body speedup circuits are coupled together in series at the second speedup node of each one of the body speedup circuits by a plurality of switch resistors such that a single switch resistor is coupled between each second speedup node of the plurality of body speedup circuits.