Amplifier module with multiple operating modes

• US 8,461,921 B2
• Filed: 09/06/2011
• Issued: 06/11/2013
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Pletcher, Nathan M, Hadjichristos, Aristotele, Nejati, Babak
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/226,400
• Publication Number:
  US 20110316637A1
• Time in Patent Office: 644 Days
• Field of Search: 330/51, 330/133, 330/150, 330/151, 330/302, 330/310
• US Class Current: 330/51
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/522 the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 2203/21136 An input signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/21139 An impedance adaptation circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21157 A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/21175 An output signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/21196 the supply voltage of a power amplifier being switchable controlled
• CPC Class Codes: H03F 2203/7206 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0088 : using discontinuously variable devices, e.g. switch-operated

Abstract

An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches.

Claims

1. An apparatus comprising:

a plurality of amplifiers;

a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode; and

an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches.

2. The apparatus of claim 1, each matching circuit in the plurality of matching circuits configured receiving a signal output from an associated amplifier.

3. The apparatus of claim 1, each matching circuit in the plurality of matching circuits configured for impedance matching between an output impedance of an associated amplifier and output impedance of the matching circuit.

4. The apparatus of claim 3, a target output impedance of the output circuit equal to a total output impedance of the plurality of matching circuits divided by a number of matching circuits in the plurality of matching circuits.

5. The apparatus of claim 1, each amplifier in the plurality of amplifiers comprising a power amplifier that is enabled in the first mode and disabled in the second mode.

6. The apparatus of claim 1, further comprising:

a first matching circuit coupled to an input of a first amplifier and a second amplifier in the plurality of amplifiers and to perform input impedance matching for each of the first amplifier and the second amplifier in the first mode; and

a second matching circuit coupled to a first switch and a second switch in the plurality of switches and to perform impedance matching in the second mode.

7. The apparatus of claim 1, the output circuit configured to perform output impedance matching and signal combining for each of the plurality of amplifiers in the first mode, receive a plurality of amplified signals and provide the output signal in the first mode, and receive a plurality of bypass signals and provide the output signal in the second mode.

8. The apparatus of claim 1, each amplifier in the plurality of amplifiers comprising a plurality of metal oxide semiconductor (MOS) transistors coupled in a stack, one of the plurality of MOS transistors receives an input signal and another one of the plurality of MOS transistors provides the amplified signal.

9. The apparatus of claim 1, each switch in the plurality of switches comprising:

a plurality of metal oxide semiconductor (MOS) transistors coupled in a stack, and

a plurality of resistors coupled to the plurality of MOS transistors and to receive a control signal to open or close the switch.

10. The apparatus of claim 1, each matching circuit in the plurality of matching circuits having an output coupled to a common node.

11. The apparatus of claim 1, each of the plurality of amplifiers, the plurality of switches, and the output circuit implemented on one or more integrated circuits.

12. The apparatus of claim 11, the plurality of matching circuits comprising:

a first matching circuit coupled to an output an associated amplifier in the plurality of amplifiers; and

at least a second matching circuit coupled to an output of an associated amplifier in the plurality of amplifiers, an output of the first matching circuit and an output of the at least a second matching circuit coupled to a common node.

13. The apparatus of claim 1, each matching circuit in the plurality of matching circuits having substantially equal input impedances.

14. The apparatus of claim 1, at least one matching circuit in the plurality of matching circuits having an input impedance different from an input impedance of at least one other matching circuit in the plurality of matching circuits.

15. The apparatus of claim 1, each matching circuit in the plurality of matching circuits coupled in parallel with every other matching circuit in the plurality of matching circuits.

16. A method of performing signal amplification, comprising:

amplifying an input signal with a plurality of amplifiers to obtain a plurality of amplified signals in a first mode;

bypassing at least one amplifier in the plurality of amplifiers with a switch coupled to an output of the at least one amplifier and providing a bypass signal in a second mode;

performing output impedance matching for each amplifier in the plurality of amplifiers with an output circuit including a plurality of matching circuits in the first mode; and

conveying an output signal based on the amplified signal in the first mode and based on the bypass signal in the second mode.

17. The method of claim 16, further comprising:

performing input impedance matching for each amplifier in the plurality of amplifiers with an associated matching circuit in the first mode; and

performing impedance matching with another matching circuit coupled to the switch in the second mode.

18. The method of claim 16, the performing output impedance matching comprising performing impedance matching between an output impedance of each amplifier in the plurality of amplifiers and a target output impedance of the output circuit.

19. The method of claim 16, the conveying an output signal comprising providing the output signal at a node coupled to an output of each matching circuit in the plurality of matching circuits.

20. An apparatus comprising:

means for amplifying an input signal with a plurality of amplifiers to obtain a plurality of amplified signals in a first mode;

means for bypassing at least one amplifier in the plurality of amplifiers with a switch coupled to an output of the at least one amplifier and providing a bypass signal in a second mode;

means for performing output impedance matching for each amplifier in the plurality of amplifiers with an output circuit including a plurality of matching circuits in the first mode; and

means for conveying an output signal based on the amplified signal in the first mode and based on the bypass signal in the second mode.