Liquid crystal display device

• US 8,462,100 B2
• Filed: 11/30/2011
• Issued: 06/11/2013
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): DINH, DUC Q
• Application Number:
  US13/307,131
• Publication Number:
  US 20120068173A1
• Time in Patent Office: 559 Days
• Field of Search: 345/57, 345/89, 345 98-100, 345/690, 345/204, 345/205, 345/206, 345/211
• US Class Current: 345/100
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133622 Colour sequential illumination
• CPC Class Codes: G02F 1/133753 with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/1393 the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells G02F1/1396, G02F1/141 take precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2310/024 Scrolling of light from the illumination source over the display in combination with the scanning of the display screen
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/342 using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3685 : Details of drivers for data electrodes
• CPC Class Codes: G11C 19/28 : using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 21/67167 : surrounding a central transfer chamber
• CPC Class Codes: H01L 27/06 : including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 : with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 : with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/15 : including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 29/247 : Amorphous materials
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H10K 2102/3023 : Direction of light emission
• CPC Class Codes: H10K 2102/3026 : Top emission
• CPC Class Codes: H10K 2102/3031 : Two-side emission, e.g. transparent OLEDs [TOLED]
• CPC Class Codes: H10K 50/8426 : Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 : the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/35 : comprising red-green-blue [RGB] subpixels
• CPC Class Codes: H10K 59/351 : comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
• CPC Class Codes: H10K 59/352 : the areas of the RGB subpixels being different
• CPC Class Codes: H10K 59/8722 : Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 71/00 : Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/421 : using coherent electromagnetic radiation, e.g. laser annealing

Abstract

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

Claims

1. A semiconductor device comprising:

a substrate;

a pixel comprising a transistor over the substrate; and

a signal line driver circuit over the substrate, the signal line driver circuit comprising;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,

wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,

wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,

wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,

wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,

wherein each of the transistor included in the pixel, the first transistor, the second transistor, the third transistor and the fourth transistor comprises;

a gate electrode;

a gate insulating layer; and

an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer including indium,

wherein the gate electrode, the gate insulating layer, and the oxide semiconductor layer are overlapped with each other and the gate insulating layer is interposed between the gate electrode and the oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein the gate insulating layer is located over the gate electrode.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer further includes a tin.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer further includes Ga and Zn.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer is formed by a-InGaZnO.

6. A display module comprising the semiconductor device according to claim 1.

7. An electronic appliance comprising the display module according to claim 6.

8. A semiconductor device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a signal line driver circuit operationally connected to the pixel, the signal line driver circuit comprising;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,

wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,

wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,

wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,

wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,

wherein each of the transistor of the pixel, the first transistor, the second transistor, the third transistor and the fourth transistor comprises;

a gate electrode;

a gate insulating layer; and

an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer including indium,

wherein the gate electrode, the gate insulating layer, and the oxide semiconductor layer are overlapped with each other and the gate insulating layer is interposed between the gate electrode and the oxide semiconductor layer.

9. The semiconductor device according to claim 8,

wherein the gate insulating layer is located over the gate electrode.

10. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer further includes a tin.

11. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer further includes Ga and Zn.

12. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer is formed by a-InGaZnO.

13. A display module comprising the semiconductor device according to claim 8.

14. An electronic appliance comprising the display module according to claim 13.

15. A semiconductor device comprising:

a pixel comprising;

a transistor; and

a pixel electrode in electrical contact with the transistor; and

a signal line driver circuit operationally connected to the pixel, the signal line driver circuit comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor;

wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC,

wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC,

wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC,

wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC,

wherein one of a source and a drain of the fifth transistor is electrically connectable to a third terminal of the driver IC,

wherein one of a source and a drain of the sixth transistor is electrically connectable to the third terminal of the driver IC,

wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line,

wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth signal line, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to a sixth signal line,

wherein each of the transistor of the pixel, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises;

a gate electrode;

a gate insulating layer; and

an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer including indium,

wherein the gate electrode, the gate insulating layer, and the oxide semiconductor layer are overlapped with each other and the gate insulating layer is interposed between the gate electrode and the oxide semiconductor layer.

16. The semiconductor device according to claim 15,

wherein the gate insulating layer is located over the gate electrode.

17. The semiconductor device according to claim 15,

wherein the oxide semiconductor layer further includes a tin.

18. The semiconductor device according to claim 15,

wherein the oxide semiconductor layer further includes Ga and Zn.

19. The semiconductor device according to claim 15,

wherein the oxide semiconductor layer is formed by a-InGaZnO.

20. A display module comprising the semiconductor device according to claim 15.

21. An electronic appliance comprising the display module according to claim 20.