Circuit for reading buttons and controlling light emitting diodes

• US 8,462,121 B1
• Filed: 02/22/2011
• Issued: 06/11/2013
• Est. Priority Date: 12/27/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Owens, Douglas W
• Assistant Examiner(s): Chen, Jianzi
• Application Number:
  US13/032,640
• Time in Patent Office: 840 Days
• Field of Search: 345/168, 345/169, 345/170, 345/172, 345/156, 315/7
• US Class Current: 345/170
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H01H 2239/012 Decoding impedances
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence

Abstract

A circuit including a first pin connection, a second pin connection, a first diode-switch arrangement and a second diode-switch arrangement. The first diode-switch arrangement is connected in series and configured to allow a current to pass from the second pin connection to the first pin connection. The second diode-switch arrangement is connected in series and configured to allow a current to pass from the first pin connection to the second pin connection. An energized state of the first and second diode-switch arrangements is determined according to a voltage detected on the first or second pin connection.

Claims

1. An apparatus comprising:

a first inverted diode pair having an anode-cathode orientation of a first diode opposite to that of the anode-cathode orientation of a second diode, the first inverted diode pair located between a first pin and a second pin;

a second inverted diode pair located between the second pin and a third pin; and

a third inverted diode pair located between the first pin and the third pin;

wherein the first inverted diode pair, the second inverted diode pair, and the third inverted diode pair are each separate from each other;

wherein the electrical states of the first pin, the second pin, and the third pin are configured to determine if current is passing through the first diode or the second diode of any of the first, the second or the third inverted diode pairs.

2. The apparatus of claim 1 where the first and second diodes in the first inverted diode pair are each connected in series to a switch which is read by setting the third pin to a high impedance state and alternately changing the state of the first and second pins by setting one of them to a low voltage, low impedance state and pulling the other to a high impedance state and measuring the voltage of the pin in the high impedance state.

3. The apparatus of claim 1 where the first and second diodes in the first inverted diode pair are light emitting diodes that are energized by setting the third pin to a high impedance state and alternately changing the state of the first and second pins to a low voltage state.

4. The apparatus of claim 3 where more than one of the light emitting diodes appear to be illuminated at the same time by increasing a frequency of the duty cycle higher than visible to a human eye.

5. The apparatus of claim 1 where the electrical states of the connection pins are sequentially controlled to determine which of the first and second diodes in each of the inverted diode pairs pass current.

6. The apparatus of claim 5 where only one of the first and second diodes pass current at any given time.

7. A method comprising:

applying a low voltage state to a first pin, wherein a first inverted diode pair is coupled between the first pin and a second pin, the first inverted diode pair including an anode-cathode orientation of a first diode opposite to that of the anode-cathode orientation of a second diode;

applying a high impedance state to a third pin, wherein a second inverted diode pair is coupled between the second pin and the third pin, wherein a third inverted diode pair is coupled between the third pin and the first pin, and wherein the first inverted diode pair, the second inverted diode pair, and the third inverted diode pair are each separate from each other;

pulling the second pin to a high voltage state to control the flow of a current between the first pin and the second pin through the first inverted diode pair; and

reading the voltage on the second pin to determine if the first diode or the second diode of the first inverted diode pair is passing the current.

8. The method of claim 7, further comprising:

after the reading the voltage on the second pin, applying a low voltage state to the second pin;

applying a high impedance state to the first pin;

pulling the third pin to a high voltage state; and

reading the voltage on the third pin to determine if current is passing through one of the diodes of the second inverted diode pair that is coupled to the third pin.

9. The method of claim 7, further comprising:

after the reading the voltage on the second pin, applying a high impedance state to the second pin;

applying a low voltage state to the third pin;

pulling the first pin to a high voltage state; and

reading the voltage on the first pin to determine if current is passing through one of the diodes of the third inverted diode pair that is coupled to the first pin.

10. The method of claim 7, wherein the low voltage state and the high voltage state are provided based on one or more pull-up resistors.

11. The method of claim 7, wherein the low voltage state and the high voltage state are provided based on one or more pull-down resistors.

12. The method of claim 7, wherein the first pin is connected to a circuit matrix row and the second pin is included in a circuit matrix column.