Method, apparatus, and system for reduction of line processing memory size used in image processing

• US 8,462,377 B2
• Filed: 07/25/2007
• Issued: 06/11/2013
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Ovsiannikov, Ilia
• Primary Examiner(s): Dulaney, Benjamin O
• Application Number:
  US11/878,605
• Publication Number:
  US 20090027727A1
• Time in Patent Office: 2,148 Days
• Field of Search: None
• US Class Current: 358/1.17
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method, apparatus, and system are provided by which image line data of an image frame is compressed before being stored to image line memory used in multiple image line processing.

Claims

1. A method of image processing, comprising:

sequentially performing a first image processing operation on each line of image data in a plurality of lines of image data;

compressing each of the lines of image data in the plurality of lines of image data;

storing each of the plurality of lines of image data in one of a plurality of line buffers;

simultaneously outputting the plurality of lines of image data from the plurality of line buffers;

simultaneously decompressing the plurality of lines of image data that are output from the plurality of line buffers to produce a plurality of decompressed lines of data; and

performing a second image processing operation on the plurality of decompressed lines of data.

2. The method of claim 1, wherein the acts of compressing, storing, and performing the first and second image processing operations are performed by circuitry on a single integrated circuit chip.

3. The method of claim 1, wherein the second image processing operation includes defect correction processing.

4. The method of claim 1, wherein the second image processing operation includes noise reduction processing.

5. The method of claim 1, wherein the second image processing operation includes optical crosstalk reduction processing.

6. The method of claim 1, wherein the second image processing operation includes demosaic processing.

7. The method of claim 1, wherein the second image processing operation includes image resizing.

8. The method of claim 1, wherein the second image processing operation includes image sharpening.

9. The method of claim 1, wherein the act of compressing comprises converting M-bit image pixel values to lesser N-bit image pixel values, where M and N are integers and N is based on a signal-to-noise ratio of the M-bit image pixel values.

10. The method of claim 9, wherein the act of compressing encodes the lines of image data based on a linear encoding function.

11. The method of claim 10, wherein the linear encoding function is a piecewise linear transform comprising two or more linear segments that map the M-bit and N-bit image pixel values to one another.

12. The method of claim 1, wherein the line buffers form a line memory of serially connected FIFO line buffers, and each of the line buffers directly outputs the stored line of image data from the line memory.

13. The method of claim 12, wherein performing the second image processing operation comprises performing the second image processing operation on the plurality of decompressed lines of image data and a line of image data being input to a sequentially first line buffer of the serially connected FIFO line buffers.

14. An imaging device, comprising:

an image sensing array for successively outputting each line of image data in a plurality of lines of image data;

a first processor circuit for sequentially performing a first image processing operation on each line of image data in the plurality of lines of image data;

a compressor for compressing the plurality of lines of image data;

a line memory having a plurality of FIFO line buffers, wherein the plurality of FIFO lines buffers are configured to serially receive each line of image data in the plurality of lines of image data and wherein the plurality of FIFO lines buffers are configured to simultaneously output the plurality of lines of image data; and

a second processor circuit for performing a second image processing operation on the plurality of lines of image data.

15. The imaging device of claim 14, further comprising:

a decompressor for decompressing the lines of image data for use by the second processor circuit.

16. The imaging device of claim 15, wherein the second processor circuit performs the second image processing operation on the decompressed lines of image data from the decompressor and a line of uncompressed image data being input to the second image processor.

17. The imaging device of claim 14, wherein the image sensing array, compressor, line memory, and second processor circuit are each part of a single integrated circuit chip.

18. The imaging device of claim 14, wherein the second image processing operation includes defect correction processing.

19. The imaging device of claim 14, wherein the second image processing operation includes noise reduction processing.

20. The imaging device of claim 14, wherein the second image processing operation includes optical crosstalk reduction processing.

21. The imaging device of claim 14, wherein the second image processing operation includes demosaic processing.

22. The imaging device of claim 14, wherein the second image processing operation includes image resizing.

23. The imaging device of claim 14, wherein the second image processing operation includes image sharpening.

24. The imaging device of claim 14, wherein the compressor converts M-bit image pixel values to lesser N-bit image pixel values, where M and N are integers and N is based on a signal-to-noise ratio of the M-bit image pixel values.

25. The imaging device of claim 24, wherein the compressor encodes the lines of image data based on a linear encoding function.

26. The imaging device of claim 25, wherein the linear encoding function is a piecewise linear transform comprising two or more linear segments that map the M-bit and N-bit image pixel values to one another.