Fast quaternary content addressable memory cell

• US 8,462,532 B1
• Filed: 01/27/2011
• Issued: 06/11/2013
• Est. Priority Date: 08/31/2010
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Argyres, Dimitri
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): BUI, THA-O H
• Application Number:
  US13/015,543
• Time in Patent Office: 866 Days
• Field of Search: 365/49.1, 365/49.17, 365/154, 711/108
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Claims

1. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:

first and second memory cells for storing the first and second data bits, respectively;

a first match line; and

a first compare circuit coupled to the first and second memory cells and the match line, and configured to discharge the first match line through one of two parallel paths between the first match line and ground potential if there is a mismatch condition between a first comparand bit and the data value, wherein each of the two parallel paths between the first match line and ground potential in the CAM cell consists of a single transistor.

2. The CAM cell of claim 1, wherein the first compare circuit comprises:

a first pull-down transistor connected between the first match line and ground potential, and having a gate responsive to a logical combination of the first comparand bit and the first data bit; and

a second pull-down transistor connected between the first match line and ground potential, and having a gate responsive to a logical combination of a complement of the first comparand bit and the second data bit, wherein the first and second pull-down transistors are in parallel with each other.

3. The CAM cell of claim 2, wherein the first compare circuit further comprises:

a first pass transistor connected between the first memory cell and the gate of the first pull-down transistor, and having a gate to receive the first comparand bit;

a first gating transistor coupled between the gate of the first pull-down transistor and ground potential, and having a gate to receive the first comparand bit;

a second pass transistor connected between the second memory cell and the gate of the second pull-down transistor, and having a gate to receive the complemented first comparand bit; and

a second gating transistor coupled between the gate of the second pull-down transistor and ground potential, and having a gate to receive the complemented first comparand bit.

4. The CAM cell of claim 3, wherein:

the first and second pull-down transistors are NMOS transistors;

the first and second gating transistors are NMOS transistors; and

the first and second pass transistors are PMOS transistors.

5. The CAM cell of claim 1, wherein the first compare circuit comprises:

a first pull-down transistor connected between the first match line and ground potential, and having a gate;

a first pass transistor connected between the first memory cell and the gate of the first pull-down transistor, and having a gate to receive the first comparand bit; and

a first gating transistor coupled between the gate of the first pull-down transistor and ground potential, and having a gate to receive the first comparand bit.

6. The CAM cell of claim 5, wherein the first compare circuit further comprises:

a second pull-down transistor connected between the first match line and ground potential, and having a gate;

a second pass transistor connected between the second memory cell and the gate of the second pull-down transistor, and having a gate to receive a complemented first comparand bit; and

a second gating transistor coupled between the gate of the second pull-down transistor and ground potential, and having a gate to receive the complemented first comparand bit.

7. The CAM cell of claim 1, further comprising:

a second match line; and

a second compare circuit coupled to the first and second memory cells and the second match line, and configured to discharge the second match line through one of two parallel paths between the second match line and ground potential if there is a mismatch condition between a second comparand bit and the data value, wherein each of the two parallel paths between the second match line and ground potential in the CAM cell consists of a single transistor.

8. The CAM cell of claim 7, wherein the first and second compare circuits compare the data value with the first and second comparand bits, respectively, at the same time.

9. The CAM cell of claim 7, wherein the first and second compare circuits compare the data value with the first and second comparand bits, respectively, in a sequential manner.

10. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:

first and second memory cells for storing the first and second data bits, respectively;

a match line; and

a compare circuit for comparing a comparand bit with the data value, the compare circuit comprising;

a first pull-down transistor connected between the match line and ground potential, and having a gate;

a first pass transistor connected between the first memory cell and the gate of the first pull-down transistor, and having a gate to receive the comparand bit; and

a first gating transistor coupled between the gate of the first pull-down transistor and ground potential, and having a gate to receive the comparand bit.

11. The CAM cell of claim 10, wherein the first data bit is selectively provided to the gate of the first pull-down transistor in response to the comparand bit.

12. The CAM cell of claim 10, wherein the compare circuit further comprises:

a second pull-down transistor connected between the match line and ground potential, and having a gate;

a second pass transistor connected between the second memory cell and the gate of the second pull-down transistor, and having a gate to receive a complemented comparand bit; and

a second gating transistor coupled between the gate of the second pull-down transistor and ground potential, and having a gate to receive the complemented comparand bit.

13. The CAM cell of claim 12, wherein the second data bit is selectively provided to the gate of the second pull-down transistor in response to a complemented comparand bit.

14. The CAM cell of claim 12, wherein:

the first and second pull-down transistors are NMOS transistors;

the first and second gating transistors are NMOS transistors; and

the first and second pass transistors are PMOS transistors.

15. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:

first and second memory cells for storing the first and second data bits, respectively;

a match line to indicate a match condition in response to compare operations between the data value and a comparand bit; and

a compare circuit coupled to the first and second memory cells and the match line, and comprising;

a first pull-down transistor connected between the match line and ground potential, and having a gate that selectively receives the first data bit in response to the comparand bit; and

a second pull-down transistor connected between the match line and ground potential, and having a gate that selectively receives the second data bit in response to a complemented comparand bit, wherein the first and second pull-down transistors are in parallel with each other.

16. The CAM cell of claim 15, wherein the compare circuit further comprises:

a first pass transistor connected between the first memory cell and the gate of the first pull-down transistor, and having a gate to receive the comparand bit;

a first gating transistor coupled between the gate of the first pull-down transistor and ground potential, and having a gate to receive the comparand bit;

a second pass transistor connected between the second memory cell and the gate of the second pull-down transistor, and having a gate to receive the complemented comparand bit; and

a second gating transistor coupled between the gate of the second pull-down transistor and ground potential, and having a gate to receive the complemented comparand bit.

17. The CAM cell of claim 16, wherein:

the first and second pull-down transistors are NMOS transistors;

the first and second gating transistors are NMOS transistors; and

the first and second pass transistors are PMOS transistors.