Flash multi-level threshold distribution scheme
First Claim
1. A method for verifying a programmed state of a flash memory cell coupled to a bitline, comprising:
- driving a wordline connected to the flash memory cell with a negative reference voltage;
determining failed programming of the flash memory cell to the programmed state if a voltage level of the bitline changes in response to the wordline at the negative reference voltage.
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Abstract
A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
67 Citations
10 Claims
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1. A method for verifying a programmed state of a flash memory cell coupled to a bitline, comprising:
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driving a wordline connected to the flash memory cell with a negative reference voltage; determining failed programming of the flash memory cell to the programmed state if a voltage level of the bitline changes in response to the wordline at the negative reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification