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Memory module with termination component

  • US 8,462,566 B2
  • Filed: 04/29/2008
  • Issued: 06/11/2013
  • Est. Priority Date: 04/24/2001
  • Status: Expired due to Term
First Claim
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1. A memory component comprising:

  • a first interface to sample address information in response to a first clock signal, the first clock signal having a first frequency, the first interface including a first plurality of inputs, each input of the first plurality of inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal; and

    a second interface to sample data in response to a second clock signal, the second clock signal having a second frequency, wherein the second frequency is at least two times the first frequency, the second interface including a second plurality of inputs, each input of the second plurality of inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

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