Memory module with termination component

• US 8,462,566 B2
• Filed: 04/29/2008
• Issued: 06/11/2013
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US12/111,816
• Publication Number:
  US 20090063887A1
• Time in Patent Office: 1,869 Days
• Field of Search: 365/194, 365/233, 365/221, 365/156
• US Class Current: 365/194
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

Claims

1. A memory component comprising:

a first interface to sample address information in response to a first clock signal, the first clock signal having a first frequency, the first interface including a first plurality of inputs, each input of the first plurality of inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal; and

a second interface to sample data in response to a second clock signal, the second clock signal having a second frequency, wherein the second frequency is at least two times the first frequency, the second interface including a second plurality of inputs, each input of the second plurality of inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

2. The memory component of claim 1 wherein the second interface includes a plurality of transmit blocks to output data referenced to a third clock signal, the third clock signal having the second frequency, each transmit block of the plurality of transmit blocks to output at least two bits of data in succession during a clock cycle of the third clock signal.

3. The memory component of claim 1 further comprising:

a first plurality of termination components, each termination component of the first plurality of termination components connected to a corresponding input of the first plurality of inputs; and

a second plurality of termination components, each termination component of the second plurality of termination components connected to a corresponding input of the second plurality of inputs.

4. The memory component of claim 1 further comprising:

an input to receive an external clock signal; and

a locked loop circuit to generate the first clock signal and the second clock signal from the external clock signal.

5. The memory component of claim 4 wherein the locked loop circuit comprises:

a first loop circuit including a first divider to generate the first clock signal according using the external clock signal in accordance with a first frequency division ratio of a frequency of the external clock signal; and

a second loop circuit including a second divider to generate the second clock signal according using the external clock signal in accordance with a second frequency division ratio of the frequency of the external clock signal.

6. The memory component of claim 5 wherein the first frequency division ratio is such that the frequency of the external clock signal is half of the first frequency , and the second frequency division ratio is one eighth of the second frequency.

7. The memory component of claim 1 further comprising a memory core including dynamic random access memory cells, wherein a clock period of the first clock signal corresponds to a memory cycle time of the memory core.

8. The memory component of claim 7 wherein the memory cycle time defines a time period between consecutive memory accesses.

9. The memory component of claim 1 wherein the first interface samples command information using the first clock signal.

10. A memory component comprising:

a first input to receive a first clock signal having a first cycle time;

a first interface to sample address information, the first interface including a first plurality of inputs, each input of the first plurality of inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal;

a second input to receive a second clock signal having a second cycle time, wherein the second cycle time is different than the first cycle time; and

a second interface including a second plurality of inputs, each input of the second plurality of inputs to transfer at least two bits of data in succession during a clock cycle of the second clock signal.

11. The memory component of claim 10 wherein the second clock signal is a strobe signal.

12. The memory component of claim 10 further comprising:

a first plurality of termination components, each termination component of the first plurality of termination components connected to a corresponding input of the first plurality of inputs; and

a second plurality of termination components, each termination component of the second plurality of termination components connected to a corresponding input of the second plurality of inputs.

13. The memory component of claim 10 further comprising a memory core including dynamic random access memory cells, wherein a clock period of the first clock signal corresponds to a memory cycle time of the memory core.

14. The memory component of claim 13 wherein the memory cycle time defines a time period between consecutive memory accesses.

15. The memory component of claim 10 wherein the first interface is used to sample command information, wherein the command information is sampled in response to the first clock signal.

16. The memory component of claim 10 wherein the at least two bits of the address information sampled in succession are associated with respective consecutive edges of the first clock signal.

17. A memory controller comprising:

a first buffer to output a first clock signal having a first cycle time;

a first transmit block to output address information to a first plurality of external conductors, wherein for each conductor of the first plurality of external conductors, the first transmit block outputs two bits of the address information during a clock cycle of the first clock signal;

a second buffer to output a second clock signal having a second cycle time, wherein the second cycle time is different than the first cycle time; and

a second transmit block to output data to a second plurality of external conductors, wherein for each conductor of the second plurality of external conductors, the second transmit block outputs at least two bits of data in succession during a clock cycle of the second clock signal.

18. The memory controller of claim 17 wherein the second transmit block includes a circuit that applies to the data, a timing offset that delays the output of the data with respect to an edge of the second clock signal.

19. The memory controller of claim 17 further comprising:

an input to receive a third clock signal having the second cycle time; and

a receive block to receive data from the second plurality of external conductors, wherein for each conductor of the second plurality of external conductors, the second transmit block receives at least two bits of data in succession during a clock cycle of the third clock signal.

20. The memory controller of claim 19 wherein the second clock signal is a write strobe signal and the third clock signal is a read strobe signal.

21. The memory controller of claim 17 wherein the first transmit block outputs control information to the plurality of external conductors.

22. The memory controller of claim 17 further comprising a locked loop circuit, the locked loop circuit including:

a first loop circuit including a first divider to generate the first clock signal from an external clock signal in accordance with a first frequency division ratio of a frequency of the external clock signal; and

a second loop circuit including a second divider to generate the second clock signal from the external clock signal in accordance with a second frequency division ratio of the frequency of the external clock signal.

23. A memory system comprising:

a first conductor to carry a first clock signal having a first cycle time;

a second conductor to carry a second clock signal having a second cycle time, wherein the second cycle time is different than the first cycle time;

a first plurality of conductors disposed alongside the first conductor, the first plurality of conductors to carry address signals;

a second plurality of conductors disposed alongside the second conductor, the second plurality of conductors to carry data associated with the address signals;

a memory controller coupled to the first conductor, second conductor, first plurality of conductors and the second plurality of conductors, the memory controller to provide the first clock signal and, for every conductor of the first plurality of conductors, two bits of the address signals during a clock cycle of the first clock signal; and

a memory component coupled to the first conductor, second conductor first plurality of conductors and the second plurality of conductors, wherein for every conductor of the second plurality of conductors, the memory device receives at least two bits of the data during a clock cycle of the second clock signal.

24. The memory system of claim 23 wherein the memory controller outputs the data onto the second plurality of conductors in accordance with a delay time to compensate for skew differences between arrival times of the data and the address signals at the memory component.

25. The memory system of claim 23 wherein the second clock signal is a strobe signal.

26. The memory system of claim 23 wherein during a memory write transaction, the memory controller outputs the data onto the second plurality of conductors.

27. The memory system of claim 23 further comprising a third conductor to carry a third clock signal having the second cycle time, wherein during a memory read transaction, for every conductor of the second plurality of conductors, the controller device receives at least two bits of data output from the memory component.

28. A memory system comprising:

a memory controller having an interface to provide;

a first clock signal over a first conductor, the a first clock signal having a first cycle time;

a second clock signal over a second conductor, the a second clock signal having a second cycle time, wherein the second cycle time is different than the first cycle time;

a plurality of address signals over a first plurality of conductors;

data signals over a second plurality of conductors; and

a memory component having an interface coupled to the first conductor, the second conductor, the first plurality of conductors and the second plurality of conductors, wherein;

for every conductor of the first plurality of conductors, the memory device receives two bits of the address signals during a clock cycle of the first clock signal; and

for every conductor of the second plurality of conductors, the memory device receives at least two bits of the data during a clock cycle of the second clock signal.

29. The memory system of claim 28 wherein the memory controller outputs the data onto the second plurality of conductors in accordance with a delay time to compensate for skew differences between arrival times of the data and the address signals at the memory component.

30. The memory system of claim 28 wherein the second clock signal is a strobe signal.

31. The memory system of claim 28 wherein during a memory write transaction, the memory controller outputs the data onto the second plurality of conductors.

32. The memory system of claim 28 further comprising a third conductor to carry a third clock signal having the second cycle time, wherein during a memory read transaction, for every conductor of the second plurality of conductors, the controller device receives at least two bits of data output from the memory component.

33. The memory system of claim 28 wherein during a memory ready transaction, the memory controller samples at least two bits of data output from the memory component in response to a delayed version of the second clock signal.

34. The memory system of claim 28 wherein the first and second clock signals are differential clock signals.