Adaptive clock recovery with step-delay pre-compensation

• US 8,462,819 B2
• Filed: 03/23/2010
• Issued: 06/11/2013
• Est. Priority Date: 01/06/2010
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Bedrosian, P. Stephan
• Primary Examiner(s): Yao, Kwang B
• Assistant Examiner(s): DUDA, ADAM K
• Application Number:
  US12/729,606
• Publication Number:
  US 20110164630A1
• Time in Patent Office: 1,176 Days
• Field of Search: 370/231, 370/235, 370/252, 370/253, 370/395, 370/395.6, 370/395.62, 370/474, 370503-520, 370/373, 375/354, 375/356, 375/371, 375/376
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56

Abstract

An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays.

Claims

1. An adaptive clock recovery (ACR) system for a receiver, the ACR system comprising:

an ACR subsystem that generates a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver;

a step-delay detection and measurement (D/M) subsystem that compares the input phase signal to the reference phase signal to detect occurrence of a step-delay in the packet arrival times and determine direction and magnitude of the detected step-delay; and

a step-delay pre-compensation component that adjusts the input phase signal, upstream of the ACR subsystem, based on the determined direction and magnitude of the detected step-delay.

2. The ACR system of claim 1, wherein the ACR subsystem comprises:

a first closed-loop control processor that generates the reference phase signal from the input phase signal;

a delay-offset estimation component that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal;

a delay-offset compensation component that generates a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and

a second closed-loop control processor that generates, from the delay-offset-compensated phase signal, an output phase signal that can be used to generate a recovered clock signal with compensated phase.

3. The ACR system of claim 2, wherein each of the first and second closed-loop control processors is a digital proportional-integral (PI) processor.

4. The ACR system of claim 2, wherein the second closed-loop control processor has a bandwidth that is greater than a bandwidth of the first closed-loop control processor.

5. The ACR system of claim 4, wherein the bandwidth of the second closed-loop control processor is at least twice the bandwidth of the first closed-loop control processor.

6. The ACR system of claim 2, wherein the second closed-loop control processor frequency filters to smooth phase discontinuities in the delay-offset-compensated phase signal.

7. The ACR system of claim 2, wherein the delay-offset estimation component determines a delay-offset value for each packet and generates the delay-offset estimate signal by identifying a largest delay-offset value within a sliding window of packets.

8. The ACR system of claim 1, wherein the step-delay D/M subsystem detects occurrence of a positive step-delay by determining that a specified number of packets within a timing window had a packet delay that exceeded a delay-floor corresponding to a set of previous packet arrival times by more than a specified delay threshold value.

9. The ACR system of claim 1, wherein the step-delay D/M subsystem detects occurrence of a negative step-delay by determining that a packet had a packet-delay below a delay-floor corresponding to a set of previous packet arrival times.

10. The ACR system of claim 1, further comprising a controller that places the ACR subsystem into a holdover mode between the detection of the step-delay and completion of the determination of the direction and magnitude of the detected step-delay.

11. The ACR system of claim 10, wherein the reference phase signal is not updated during the holdover mode.

12. The ACR system of claim 10, wherein the output phase signal is not updated during the holdover mode.

13. The ACR system of claim 1, wherein the step-delay D/M subsystem determines a magnitude of a positive step-delay by generating, for each packet in a timing window, a delay-shift value relative to the reference phase signal in holdover mode corresponding to a set of previous packet arrival times and determining, for the timing window, a minimum delay-shift value representing the magnitude of the positive step-delay.

14. The ACR system of claim 13, wherein:

after the step-delay D/M subsystem determines the magnitude of the positive step-delay, the step-delay D/M subsystem (i) includes a value of the magnitude in a history of previous step-delays and (ii) uses the value of the magnitude to update a step-delay estimate signal used by the step-delay pre-compensation unit to adjust the input phase signal; and

after the step-delay pre-compensation unit applies the updated step-delay estimate signal, the ACR subsystem is taken out of holdover mode and placed into normal operating mode.

15. The ACR system of claim 14, wherein, if packets stop arriving at the receiver for a specified period of time to create a loss-of-signal condition for the ACR subsystem, then the history of previous step-delays is set to a value of 0.

16. The ACR system of claim 1, wherein the step-delay D/M subsystem determines a magnitude of a negative step-delay by generating, for each packet in a timing window, a delay-offset value relative to the reference phase signal in holdover mode corresponding to a set of previous packet arrival times and determining, for the timing window, a maximum delay-offset value representing the magnitude of the negative step-delay.

17. The ACR system of claim 16, wherein:

after the step-delay D/M subsystem determines the magnitude of the negative step-delay, the step-delay D/M subsystem (i) includes a value of the magnitude in a history of previous step-delays and (ii) uses the value of the magnitude to update a step-delay estimate signal used by the step-delay pre-compensation unit to adjust the input phase signal; and

after the step-delay pre-compensation unit applies the updated step-delay estimate signal, the ACR subsystem is taken out of holdover mode and placed into normal operating mode.

18. The ACR system of claim 17, wherein, if packets stop arriving at the receiver for a specified period of time to create a loss-of-signal condition for the ACR subsystem, then the history of previous step-delays is set to a value of 0.

19. A receiver-implemented method for recovering a clock signal at a receiver in a packet system, the method comprising:

generating a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver;

comparing the input phase signal to the reference phase signal to detect the occurrence of a step-delay in the packet arrival times and determine direction and magnitude of the detected step-delay; and

adjusting the input phase signal, upstream of the generation of the reference phase signal, based on the determined direction and magnitude of the detected step-delay.