Performing mathematical and logical operations in multiple sub-cycles

• US 8,463,836 B1
• Filed: 11/07/2005
• Issued: 06/11/2013
• Est. Priority Date: 11/07/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Pugh, Daniel J., Redgrave, Jason, Caldwell, Andrew
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US11/269,869
• Time in Patent Office: 2,773 Days
• Field of Search: 708/230.232, 708/518
• US Class Current: 708/518
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation.

Claims

1. An integrated circuit (“

IC”

) comprising;

a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle, wherein the IC implements a design that is designed for a design clock having an associated design cycle, wherein each reconfiguration cycle has a smaller duration than the design cycle, wherein at least one operand of the mathematical operation has n bits, wherein to perform the mathematical operation, the set of reconfigurable circuits (i) receives a first configuration data set during a first reconfiguration cycle to configure said set of reconfiguration circuits to perform a first sub-operation on m of n bits and (ii) receives a second configuration data set during a second reconfiguration cycle to configure said set of reconfiguration circuits to perform a second sub-operation on p of n bits, wherein the first reconfiguration cycle and the second reconfiguration cycle are consecutive reconfiguration cycles; and

at least one storage element for storing at least a portion of a result produced by the first sub-operation during the first reconfiguration cycle for use in the second sub-operation during the second reconfiguration cycle.

2. The IC of claim 1, wherein the set of reconfigurable circuits further performs a third sub-operation on q of n bits in a third reconfiguration cycle, wherein the set of reconfigurable circuits further receives a third configuration data set during the third reconfiguration cycle to perform part of the third sub-operation.

3. The IC of claim 1, wherein the storage element is an interconnect/storage circuit that interconnects circuits of the IC when acting as an interconnect circuit and stores data when acting as a storage circuit.

4. The IC of claim 1, wherein the storage element stores said portion of the result produced by the first sub-operation until the end of the second sub-operation and discards the portion of the result after the end of the second sub-operation.

5. The IC of claim 1, wherein said portion of the result of the first sub-operation is a first portion of the result produced by the first sub-operation, wherein the storage element is a first storage element, the IC further comprising a second storage element for storing a second portion of the result produced by the first sub-operation until the mathematical operation is completed.

6. The IC of claim 1, wherein a particular sub-set of the set of reconfigurable circuits performs both the first sub-operation and the second sub-operation.

7. The IC of claim 1, wherein said set of reconfigurable circuits performs a plurality of mathematical operations in a first plurality of reconfiguration cycles and performs a plurality of logical operations in a second plurality of reconfiguration cycles.

8. The IC of claim 7, wherein said plurality of logical operations are non-arithmetic operations.

9. The IC of claim 1, wherein the set of reconfigurable circuits includes more than one reconfigurable circuit.

10. The IC of claim 1, wherein the mathematical operation is an addition operation.

11. The IC of claim 1, wherein the mathematical operation is a subtraction operation.

12. The IC of claim 1, wherein the mathematical operation is a multiplication operation.

13. The IC of claim 1, wherein each of a plurality of reconfigurable circuits in the set of reconfigurable circuits (i) receives part of the first configuration data set during the first reconfiguration cycle to perform a part of the first sub-operation and (ii) receives part of the second configuration data set during the second reconfiguration cycle to perform a part of the second sub-operation.

14. The IC of claim 1, wherein said set of reconfigurable circuits comprises a set of look-up-tables (“

LUTs”

).

15. The IC of claim 1, wherein the set of reconfigurable circuits further receives a third configuration data set during a third reconfiguration cycle to perform a logical operation, wherein the third reconfiguration cycle is immediately after the second reconfiguration cycle.

16. An electronics system comprising:

an integrated circuit (“

IC”

) comprising;

a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle, wherein the IC implements a design that is designed for a design clock having an associated design cycle, wherein each reconfiguration cycle has a smaller duration than the design cycle, wherein at least one operand of the mathematical operation has n bits, wherein to perform the mathematical operation, the set of reconfigurable circuits (i) receives a first configuration data set during a first reconfiguration cycle to configure said set of reconfiguration circuits to perform a first sub-operation on m of n bits and (ii) receives a second configuration data set during a second reconfiguration cycle to configure said set of reconfiguration circuits to perform a second sub-operation on p of n bits, wherein the first reconfiguration cycle and the second reconfiguration cycle are consecutive reconfiguration cycles; and

at least one storage element for storing at least a portion of a result produced by the first sub-operation during the first reconfiguration cycle for use in the second sub-operation during the second reconfiguration cycle.

17. The electronics system of claim 16, wherein the set of reconfigurable circuits further performs a third sub-operation on q of n bits in a third reconfiguration cycle, wherein the set of reconfigurable circuits further receives a third configuration data set during the third reconfiguration cycle to perform the third sub-operation.

18. The electronics system of claim 16, wherein the storage element is an interconnect/storage circuit that interconnects circuits of the IC when acting as an interconnect circuit and stores data when acting as a storage circuit.

19. The electronics system of claim 16, wherein the storage element stores said portion of the result of the first sub-operation until the end of the second sub-operation and discards the portion of the result after the end of the second sub-operation.

20. The electronics system of claim 16, wherein said portion of the result produced by the first sub-operation is a first portion of the result produced by the first sub-operation, wherein the storage element is a first storage element, the IC further comprising a second storage element for storing a second portion of the result produced by the first sub-operation until the mathematical operation is completed.

21. The electronics system of claim 16 further comprising a non-volatile memory for storing configuration data and for supplying configuration data to the IC when the IC powers up.

22. The electronics system of claim 21, wherein the non-volatile memory and the IC are on different IC dies.

23. The electronics system of claim 21, wherein the non-volatile memory and the IC are on a same IC die.

24. The electronics system of claim 16, wherein each of a plurality of reconfigurable circuits in the set of reconfigurable circuits (i) receives part of the first configuration data set during the first reconfiguration cycle to perform a part of the first sub-operation and (ii) receives part of the second configuration data set during the second reconfiguration cycle to perform a part of the second sub-operation.

25. The electronics system of claim 16, wherein said set of reconfigurable circuits performs a plurality of mathematical operations in a first plurality of reconfiguration cycles and performs a plurality of logical operations in a second plurality of reconfiguration cycles.

26. The electronics system of claim 16, wherein said set of reconfigurable circuits comprises a set of look-up-tables (“

LUTs”

).

27. A method for performing mathematical operations of a user design, said method comprising:

receiving a set of operands at a set of reconfigurable circuits of an integrated circuit (“

IC”

), said set of reconfigurable circuits for reconfigurably performing an operation on said set of operands in more than one reconfiguration cycle, wherein the user design is designed for a design clock having an associated design cycle, wherein each reconfiguration cycle has a smaller duration than the design cycle;

receiving a first set of configuration data for configuring said set of reconfigurable circuits to perform a first sub-operation of said operation;

performing said first sub-operation during a first reconfiguration cycle;

receiving a second set of configuration data for reconfiguring said set of reconfigurable circuits to perform a second sub-operation of said operation; and

performing said second sub-operation during a second reconfiguration cycle,

wherein the first reconfiguration cycle and the second reconfiguration cycle are consecutive reconfiguration cycles.

28. The method of claim 27 further comprising:

receiving a third set of configuration data for reconfiguring said set of reconfigurable circuits to perform a set of logic operations; and

performing said set of logic operations during a third reconfiguration cycle immediately after the second reconfiguration cycle.

29. The method of claim 28, wherein each of the first, second and third reconfiguration cycle is a separate reconfiguration subcycle of said user design cycle.

30. The method of claim 27, wherein said set of reconfigurable circuits comprise a set of look-up-tables (“

LUTs”

).