Method and apparatus for data transmission between processors using memory remapping

• US 8,464,006 B2
• Filed: 02/07/2008
• Issued: 06/11/2013
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kwon, Young-Su, Kim, Hyuk, Baek, Young-Seok, Lee, Suk Ho, Koo, Bon Tae, Eum, Nak Woong
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): CARDWELL, ERIC
• Application Number:
  US12/027,364
• Publication Number:
  US 20080270711A1
• Time in Patent Office: 1,951 Days
• Field of Search: 711/147, 711/165, 711/E12.066
• US Class Current: 711/148
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems

Abstract

Provided are a method and apparatus for efficiently transferring a massive amount of multimedia data between two processors. The apparatus includes a first local switch, which connects a virtual page of a first processor element to a shared memory page, a second local switch, which connects a virtual page of a second processor element to the shared memory page, a shared page switch, which connects a predetermined shared memory page of a shared physical memory to the first or second local switch, and a switch manager, which remaps a certain shared memory page of the shared physical memory that stores data of a task performed by the first processor element to the virtual page of the second processor element. Accordingly, since memory remapping is used, the massive amount of multimedia data can be transmitted by changing a method of mapping a memory, unlike a case when multimedia data is transmitted by using a memory bus.

Claims

1. An apparatus for performing data transmission between processors using memory remapping in a multiprocessor system including a plurality of processor elements, the apparatus comprising:

a first local switch of a first processor element having a control input coupled to a switch manager to receive control instructions from the switch manager to selectively connect a virtual page of the first processor element to a shared memory page of a shared physical memory that is shared by the first processor element and a second processor element;

a second local switch of the second processor element having a control input coupled to the switch manager to receive control instructions from the switch manager to selectively connect a virtual page of the second processor element to the shared memory page of the shared physical memory;

a shared page switch having a control input coupled to the switch manager to receive control instructions from the switch manager to selectively connect the shared memory page of the shared physical memory to the first local switch or the second local switch; and

the switch manager selectively transmitting control instructions to the control inputs of the first local switch, the second local switch, and the shared page switch to remap a certain shared memory page of the shared physical memory storing data of a task performed by the first processor element to the virtual page of the second processor element and to remap an idle shared memory page of the shared physical memory to the virtual page of the first processor element, when the task performed by the first processor element and a task performed by the second processor element are completed.

2. The apparatus of claim 1, wherein the first processor element and the second processor element are processor elements of a stream processor for processing a multimedia data stream.

3. The apparatus of claim 1, wherein the switch manager comprises:

a task synchronizer, which synchronizes the tasks by determining whether the tasks that are performed by the first and second processor elements are completed; and

a switch controller, which controls the first local switch, the second local switch, and the shared page switch.

4. The apparatus of claim 3, wherein the task synchronizer transmits a control start instruction to the switch controller based on a time of receiving task completion notification from both first and second processor elements.

5. The apparatus of claim 1, wherein the switch manager remaps a shared memory page, which is in an idle state after being mapped to the virtual page of the second processor element and then unmapped, to the virtual page of the first processor element.

6. A method of performing data transmission between processors using memory remapping in a multiprocessor system including a plurality of processor elements, the method comprising:

transmitting, from a switch manager to a shared page switch, a first control message to selectively connect a virtual memory page of a first processor element to a first shared memory page of a shared physical memory that is shared by the first processor element and a second processor element;

connecting, by the shared page switch, the virtual memory page of the first processor element to the first shared memory page of the shared physical memory in response to receiving the first control message;

storing first data, which is obtained from the first processor element performing a first task, in the first shared memory page, which is connected to the virtual memory page of the first processor element by the shared page switch;

when the first task performed by the first processor element and a task performed by the second processor element are completed, transmitting, from the switch manager to the shared page switch, a second control message to selectively connect the first shared memory page storing the first data to a virtual memory page of the second processor element, and selectively connect a second shared memory page of the shared physical memory to the virtual memory page of the first processor element;

connecting, by the shared page switch, the first shared memory page to the virtual memory page of the second processor element, and the second shared memory page to the virtual memory page of the first processor element, in response to receiving the second control message; and

obtaining second data from the second processor element performing a second task based on the first data stored in the first shared memory page connected to the virtual memory page of the second processor by the shared page switch.

7. The method of claim 6, wherein the first processor element and the second processor element are processor elements of a stream processor for processing a multimedia data stream.

8. The method of claim 6, further comprising synchronizing the tasks by determining whether the tasks that are performed by the first and second processor elements are completed.

9. The method of claim 8, wherein the synchronizing of the tasks comprises transmitting a control start instruction for memory remapping based on a time of receiving task completion notifications from both first and second processor elements.

10. The method of claim 6, wherein the remapping remaps a shared memory page, which is in an idle state after being mapped to the virtual page of the second processor element and then unmapped, to the virtual page of the first processor element.

11. The method of claim 6, wherein the shared page switch is operative to connect each of the first and second shared memory pages of the shared physical memory to a virtual memory page of either the first or the second processor element.