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Methods and systems for diagnosing hardware and software faults using time-stamped events

  • US 8,464,102 B2
  • Filed: 12/23/2010
  • Issued: 06/11/2013
  • Est. Priority Date: 12/23/2010
  • Status: Active Grant
First Claim
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1. A method executed by a computer processor of an observing device for classifying faults in an electronic network utilizing a time-triggered communication system and a high-resolution time component, the method comprising:

  • (i) the processor receiving a first fault code generated at a first task of the electronic system in response to a first fault at the first task, wherein the first fault code identifies;

    a first communication cycle of the electronic system associated with the first fault; and

    a first slot, corresponding to the first task, of a first message in which the first fault code is transmitted to the processor;

    (ii) the processor receiving a second fault trouble code generated at a second faulting task of the electronic system in response to a second fault, wherein the second fault code identifies;

    a second communication cycle of the electronic system associated with the second fault; and

    a second slot, corresponding to the second task, of a second message in which the second fault code is transmitted to the processor,wherein the first slot and the second slot are populated with the first fault code and the second fault code, respectively, based on time synchronized with respect to the high-resolution time component;

    (iii) the processor identifying an execution cycle offset associated with the first task and the second task using an execution schedule;

    (iv) the processor considering whether the first cycle, of the first fault trouble code, is separated from the second cycle, of the second fault trouble code, by the execution cycle offset identified by the schedule;

    (v) if the processor determines that the first cycle is not separated from the second cycle by the execution cycle offset, the processor further determining that the first fault did not cause the second fault;

    (vi) if the processor determines that the first cycle is separated from the second cycle by the execution cycle offset, the processor considering whether operation of any of the tasks is dependent on operation of any other of the tasks based on task-dependency data;

    (vii) if the processor determines that operation of none of the tasks is dependent on operation of another of the tasks, the processor further determining that the first fault and the second fault are coincidental;

    (viii) if the processor determines that operation of at least one of the tasks is dependent on operation of at least one other of the tasks, the processor considering whether operation of the second task is dependent on operation of the first task;

    (ix) if the processor determines that operation of the second task is dependent on operation of the first task, the processor further determining that the failure of the first task caused the failure in the second task; and

    (x) if the processor determines that operation of the second task is not dependent on operation of the second task, the processor further determining that the first fault did not cause the second fault.

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