Integrated circuit having direction dependent wiring

• US 8,464,187 B1
• Filed: 07/12/2012
• Issued: 06/11/2013
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: IYM Technologies LLC (General Patent Corporation)
• Original Assignee: IYM Technologies LLC (General Patent Corporation)
• Inventors: Qian, Qi-De
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/547,444
• Time in Patent Office: 334 Days
• Field of Search: 716/52, 716 54- 55
• US Class Current: 716/54
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.

Claims

1. An integrated circuit product comprising:

a plurality of connection points;

at least one layer comprising routing wires connecting said connection points;

a first set of routing wires in said layer connecting along a first direction;

a second set of routing wires in said layer connecting along a second direction, said second direction being orthogonal to said first direction; and

said first set of routing wires having wire width values substantially different from the wire width values of said second set of routing wires.

2. The integrated circuit product of claim 1, wherein said first set of routing wires have wire to wire spacing values substantially different from the wire to wire spacing values of said second set of routing wires.

3. The integrated circuit product of claim 1, wherein one or more wire segments in said first set of routing wires abut one or more wire segments in said second set of routing wires, whereby forming bending wires having substantially different wire width values between connected orthogonal wire segments.

4. The integrated circuit product of claim 1, wherein said first direction rotates by 90 degrees between adjacently located said layers.

5. The integrated circuit product of claim 1, wherein said first direction coincides with a predefined preferred routing direction.

6. The integrated circuit product of claim 1, wherein said first set of routing wires have a minimal wire width value that is substantially smaller than the minimal wire width value of said second set of routing wires.

7. The integrated circuit product of claim 1, wherein said first set of routing wires have a minimal wire to wire spacing value that is substantially smaller than the minimal wire to wire spacing value of said second set of routing wires.

8. The integrated circuit product of claim 1, wherein said second set of routing wires consisting essentially of wires having larger widths than wires in said first set of wires.

9. The integrated circuit product of claim 1, wherein said second set of routing wires consisting essentially of wires having larger wire to wire spacing than wires in said first set of wires.

10. An integrated circuit product comprising:

a chip area comprising a plurality of vias;

at least one metal layer comprising metal wires connecting said vias;

a first set of said metal wires connecting along a first direction;

a second set of said metal wires connecting along a second direction, said second direction being orthogonal to said first direction; and

said first set of said metal wires having substantially different wire width from said second set of said metal wires.

11. The integrated circuit product of claim 10, wherein said first set of said metal wires have substantially different pitch from said second set of said metal wires.

12. The integrated circuit product of claim 10, wherein one or more wire segments in said first set of said metal wires abut one or more wire segments in said second set of said metal wires, whereby forming one or more bending wires having substantially different wire width values between abutted orthogonal wire segments.

13. The integrated circuit product of claim 10, wherein said first direction rotates by 90 degrees between adjacently located said at least one metal layers.

14. The integrated circuit product of claim 10, wherein said first direction coincides with a predefined preferred routing direction.

15. The integrated circuit product of claim 10, wherein said second set of said metal wires having a minimal wire width value substantially larger than the minimal wire width value of said first set of said metal wires.

16. The integrated circuit product of claim 10, wherein said second set of said metal wires having a minimal pitch substantially larger than the minimal pitch of said first set of said metal wires.

17. The integrated circuit product of claim 10, wherein said second set of metal wires consisting essentially of wires having substantially larger wire width values than wires in said first set of wires.

18. The integrated circuit product of claim 10, wherein said second set of metal wires consisting essentially of wires having substantially larger pitch than wires in said first set of wires.

19. An integrated circuit product prepared by a process comprising the steps of:

providing a plurality of connection points;

providing at least one metal layer comprising routing wires;

loading a first wire width constraint for a first set of routing wires oriented along a first direction in said metal layer;

loading a substantially different second wire width constraint for a second set of routing wires oriented along a second direction in said metal layer, said second direction being orthogonal to said first direction; and

functionally connecting said connection points using said first set of routing wires along said first direction, and using said second set of routing wires along said second direction.

20. The integrated circuit product of claim 19, further comprising the steps of:

loading a first pitch constraint for said first set of routing wires; and

loading a substantially different second pitch constraint for said second set of routing wires.