Semiconductor device structures and related processes

• US 8,466,025 B2
• Filed: 08/01/2011
• Issued: 06/18/2013
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N.
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/195,154
• Publication Number:
  US 20110298043A1
• Time in Patent Office: 687 Days
• Field of Search: 438/270, 438/197, 438/466, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.

Claims

1. A method for operating a semiconductor device structure, comprising:

controlling conduction between first and second source/drain electrodes through a channel location in semiconductor material using a gate electrode positioned in a first trench to provide at least ON and OFF states; and

avoiding punchthrough of said channel location, using both

one or more recessed field plates, positioned in proximity to and capacitively coupled to said semiconductor material;

said recessed field plates being positioned in respective second trenches, and

one or more diffusion components of a second conductivity type lying at least partially directly beneath said respective second trenches;

whereby said diffusion components reduce depletion spreading in the OFF state.

3. The method of claim 1, wherein the gate has a split poly configuration.

4. The method of claim 1, wherein at least one of the recessed field plates has a split poly configuration.

5. The method of claim 1, wherein both the gate and at least one of the recessed field plates have a split poly configuration.

6. The method of claim 1, wherein said gate is capacitively coupled to control vertical conduction to a drain diffusion of a first conductivity type.

2. A method for operating a semiconductor device structure, comprising:

controlling conduction between first and second source/drain electrodes through a channel location in semiconductor material using a gate electrode positioned in a first trench to provide at least ON and OFF states; and

avoiding punchthrough of said channel location, using both

one or more recessed field plates, positioned in proximity to and capacitively coupled to said semiconductor material;

said recessed field plates being positioned in respective second trenches, and

one or more diffusion components of a second conductivity type lying at least partially directly beneath said respective second trenches;

whereby said diffusion components reduce depletion spreading in the OFF state;

wherein said device further includes a layer of dopant concentration region of second-conductivity-type that extends from a source layer to at least one location of said diffusion components.

7. A fabrication process for making a MOSFET, comprising the actions, in any order, of:

a) providing an n-type semiconductor layer;

b) forming a p-type body in said layer;

c) forming an n-type source, which is isolated by said body, in said layer;

d) forming an insulated gate trench in said layer, and a gate electrode in said gate trench;

said gate electrode being capacitively coupled to at least a portion of said body;

e) forming a second insulated trench in said layer, providing an additional dose of acceptor dopants below said trench, and forming a Recessed Field Plate electrode in said second trench; and

f) providing an additional dose of donor dopant atoms in said portion of said body, to thereby reduce the on-resistance.