Method for producing a thin chip comprising an integrated circuit
First Claim
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1. A method for producing a plurality of thin film chips, each comprising an integrated circuit, the method comprising the steps of:
- providing a semiconductor wafer having a top side and a bottom side,producing a plurality of closed hidden wafer cavities near the top side, said closed hidden wafer cavities each having a lateral area extent that defines the chip area of one of said thin film chips above the respective wafer cavity, such that each chip area is substantially unsupported beneath the chip area,producing at least one integrated circuit structure in at least one defined chip area suspended above a respective wafer cavity, andseparating the defined chip area from the semiconductor wafer,wherein the step of separating includes a first process sequence, wherein a plurality of trenches down to the closed hidden cavities are produced along a substantial majority portion of the entire lateral periphery of said defined chiparea such that the defined chip area is primarily held on the semiconductor wafer via separated, residual web-like connections, which are arranged at the lateral periphery of said chip area above the respective wafer cavity, andwherein the web-like connections are severed in a second process sequence by breaking the web-like connections.
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Abstract
In a method for producing a very thin chip including an integrated circuit, a circuit structure is produced in a defined section of a semiconductor wafer. The defined wafer section is subsequently released from the semiconductor wafer. For this purpose, the wafer section is firstly freed such that it is held only via local web-like connections on the remaining semiconductor wafer, which web-like connections are arranged at a lateral periphery of the wafer section. The web-like connections are subsequently severed.
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18 Claims
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1. A method for producing a plurality of thin film chips, each comprising an integrated circuit, the method comprising the steps of:
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providing a semiconductor wafer having a top side and a bottom side, producing a plurality of closed hidden wafer cavities near the top side, said closed hidden wafer cavities each having a lateral area extent that defines the chip area of one of said thin film chips above the respective wafer cavity, such that each chip area is substantially unsupported beneath the chip area, producing at least one integrated circuit structure in at least one defined chip area suspended above a respective wafer cavity, and separating the defined chip area from the semiconductor wafer, wherein the step of separating includes a first process sequence, wherein a plurality of trenches down to the closed hidden cavities are produced along a substantial majority portion of the entire lateral periphery of said defined chiparea such that the defined chip area is primarily held on the semiconductor wafer via separated, residual web-like connections, which are arranged at the lateral periphery of said chip area above the respective wafer cavity, and wherein the web-like connections are severed in a second process sequence by breaking the web-like connections. - View Dependent Claims (2, 3, 4, 5, 6, 18)
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7. A method for producing a thin film chips, each comprising an integrated circuit, the method comprising the steps of:
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providing a semiconductor wafer having a top surface and a bottom surface, the semiconductor wafer being composed of a first semiconductor material at the top surface, defining a plurality of chip areas at the top surface, with each chip area having a lateral periphery that defines one of said thin film chips, producing at least one integrated circuit structure in at least one defined chip area, and releasing the defined chip area from the semiconductor wafer, wherein the step of defining the plurality of chip areas comprises a step of producing a plurality of closed wafer cavities below the top surface by producing a plurality of porous regions in the first semiconductor material, with each porous region laterally extending below and matching a defined chip area such that each chip area ia substantially unsupported beneath the chip area, and by producing a voer layer covering the porour regions so as to form the closed wafer cavities below the top surface, wherein the defined chip area is freed in a first process sequence such that the chip area is held on the remaining semiconductor wafer primarily via spaced apart web-like connections in said cover layer, which are arranged along minor portions of the lateral periphery above the respective wafer cavity, and wherein the web-like connections are severed in a second process sequence. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification