Multi-layer interconnect structure for stacked dies

• US 8,466,059 B2
• Filed: 03/30/2010
• Issued: 06/18/2013
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Chiu, Chien-Ming, Wu, Tsang-Jiuh, Shue, Shau-Lin, Yu, Chen-Hua
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US12/750,100
• Publication Number:
  US 20110241217A1
• Time in Patent Office: 1,176 Days
• Field of Search: 438/667, 438/622, 438/618, 438/459, 438/455, 257/E21.577, 257/E21.585
• US Class Current: 438/667
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a first substrate, the first substrate having a through-substrate via extending from a first side into the first substrate;

exposing the through-substrate via on a second side of the first substrate, the through-substrate via extending beyond a surface on the second side of the first substrate by a first distance;

forming a first isolation film having a thickness less than the first distance, the first isolation film formed along the second side of the first substrate such that the through-substrate via is exposed;

forming a first conductive element on the through-substrate via, the first conductive element extending over an upper surface of the first isolation film;

forming a second isolation film on the first isolation film and the first conductive element; and

forming a second conductive element electrically coupled to the first conductive element, the second conductive element extending over the upper surface of the second isolation film.

2. The method of claim 1, wherein the forming the first conductive element comprises:

forming a seed layer over the first isolation film and the through-substrate via;

forming a patterned mask over the seed layer, the patterned mask exposing portions of the seed layer;

forming a metal pad over exposed portions of the seed layer;

removing the patterned mask; and

removing exposed portions of the seed layer.

3. The method of claim 2, wherein the forming the metal pad is performed at least in part by electroplating.

4. The method of claim 1, further comprising forming a third isolation film over the second isolation film and the second conductive element and forming a connection element electrically coupled to the second conductive element.

5. The method of claim 4, wherein the forming the third isolation film comprises using a self-planarization technique.

6. The method of claim 1, wherein the forming the second isolation film comprises using a self-planarization technique.

7. The method of claim 1, wherein the exposing the through-substrate via comprises etching the first substrate below a surface of the through-substrate via such that the through-substrate via protrudes from the first substrate.

8. A method of forming a semiconductor device, the method comprising:

providing a substrate having one or more through-substrate vias extending from a circuit-side to a backside of the substrate;

forming a first redistribution layer, the forming the first redistribution layer comprising;

forming a first isolation film over the backside of the substrate;

exposing at least a portion of the one or more through-substrate vias, the exposing comprising recessing the backside of the substrate such that the through-substrate vias protrude from the backside of the substrate; and

forming first conductive elements electrically coupled to respective ones of the one or more through-substrate vias, the first conductive elements extending over an upper surface of the first isolation film; and

forming one or more additional redistribution layers, the forming of each additional redistribution layer comprising;

forming an additional isolation film over an uppermost isolation film;

exposing at least a portion of underlying conductive elements in an underlying layer; and

forming additional conductive elements electrically coupled to respective ones of the underlying conductive elements, the additional conductive elements extending over an upper surface of the respective additional isolation film.

9. The method of claim 8, wherein the forming the first conductive elements comprises:

forming a seed layer over the one or more through-substrate vias;

forming a patterned mask over the seed layer, the patterned mask exposing portions of the seed layer;

forming a conductive pad over the exposed portions of the seed layer; and

removing the patterned mask.

10. The method of claim 8, wherein the forming the first conductive elements uses photoresist materials and photolithography techniques, and further comprising stripping the photoresist materials and cleaning exposed portions of the first isolation film.

11. The method of claim 8, wherein the forming the first conductive elements is performed at least in part by electroplating.

12. A method of forming a semiconductor device, the method comprising:

providing a first substrate, the first substrate having a through-substrate via extending from a first side into the first substrate, the through-substrate via extending beyond a surface on the second side of the first substrate;

forming a first isolation film along the second side of the first substrate, the through-substrate via exposed through the first isolation film;

forming a first conductive element on the through-substrate via, the first conductive element extending over an upper surface of the first isolation film;

forming a second isolation film on the first isolation film and the first conductive element; and

forming a second conductive element electrically coupled to the first conductive element, the second conductive element extending over the upper surface of the second isolation film.

13. The method of claim 12, wherein the providing the substrate comprises reducing the first substrate below a surface of the through-substrate via such that the through-substrate via protrudes from the surface on the second surface of the first substrate.

14. The method of claim 12, wherein the forming the first conductive element comprises:

forming a patterned mask exposing portions of the first isolation film and through-substrate via; and

forming a metal pad over at least the exposed portions of the first isolation film and through-substrate via.

15. The method of claim 12, wherein the forming a first isolation film comprises reducing the first isolation film to expose the through-substrate via.

16. The method of claim 12, wherein the forming the metal pad is performed at least in part by electroplating.

17. The method of claim 12, further comprising forming a third isolation film over the second isolation film and the second conductive element and forming a connection element electrically coupled to the second conductive element.

18. The method of claim 12, wherein providing a first substrate comprises providing a liner disposed between the through-substrate via and the substrate.

19. The method of claim 18, wherein the forming a first isolation film comprises reducing the first isolation film and the liner to expose the through-substrate via.