Thin film transistor and method of fabricating the same

• US 8,466,462 B2
• Filed: 02/11/2009
• Issued: 06/18/2013
• Est. Priority Date: 08/21/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Chung, Hyun-Joong, Kim, Min-Kyu, Jeong, Jong-Han, Mo, Yeon-Gon
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US12/369,051
• Publication Number:
  US 20100044699A1
• Time in Patent Office: 1,588 Days
• Field of Search: 257/43, 257/49, 257/52, 257/59, 257/40, 257/103, 257/289, 257/66, 257/79, 257/E51.005, 257/E29.151, 257/E27.1, 257/E29.117, 257/E29.137, 257/E29.182, 257/E29.202, 257/E33.004, 257/E31.034, 257/E31.047, 257/E31.051, 257/E21.411, 257/72, 257/E29.296, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT) including a gate electrode, an active layer, and source and drain electrodes. The active layer includes contact regions that contact the source and drain electrodes, which are thinner than a remaining region of the active layer. The contact regions reduce the contact resistance between the active material layer and the source and drain electrodes.

Claims

1. A thin film transistor (TFT) comprising:

a gate electrode;

an active layer overlapping the gate electrode, having contact regions that have a consistent thickness, and a remaining region that is thicker than the contact regions;

an etch stop layer covering the remaining region and exposing the contact regions; and

source and drain electrodes contacting the contact regions and directly contacting opposing surfaces of the remaining region.

2. The thin film transistor as claimed in claim 1, wherein the thickness of the contact regions is from about 10% to 90% of the thickness of the remaining region.

3. The thin film transistor as claimed in claim 1, wherein the active layer comprises an oxide semiconductor.

4. The thin film transistor as claimed in claim 3, wherein the active layer comprises an amorphous oxide having an electron carrier density of less than about 10¹⁸/cm³.

5. The thin film transistor as claimed in claim 4, wherein the amorphous oxide comprises at least one selected from the group consisting of:

an oxide comprising In, Zn, and Sn;

an oxide comprising In, Zn, and Ga;

or an oxide comprising at least one selected from the group consisting of Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, P, Ti, Zr, Hf, V, Ru, Ge, Sn, and F.

6. The thin film transistor as claimed in claim 1, wherein the TFT has a bottom gate structure.

7. The thin film transistor as claimed in claim 6, wherein the source and drain electrodes directly contact the contact regions of the active layer.

8. The thin film transistor as claimed in claim 1, further comprising an interface stabilizing layer formed under the active layer, comprising an oxide having a band gap greater than, or equal to, the band gap of the active layer.