Thin film transistor having an oxide semiconductor bilayer, method of manufacturing the same and flat panel display device having the same

• US 8,466,465 B2
• Filed: 03/23/2009
• Issued: 06/18/2013
• Est. Priority Date: 08/04/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jeong, Jong-Han, Ahn, Tae-Kyung, Jeong, Jae-Kyeong, Park, Jin-Sung, Lee, Hun-Jung, Shin, Hyun-Soo, Mo, Yeon-Gon
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/382,743
• Publication Number:
  US 20100026169A1
• Time in Patent Office: 1,548 Days
• Field of Search: 257/57, 257/59, 257/66, 257/69, 257/72, 257/E29.151, 257/E29.117, 257/E29.137, 257/E29.202, 257/E29.273
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Disclosed is a thin film transistor which has an oxide semiconductor as an activation layer, a method of manufacturing the same and a flat panel display device having the same. The thin film transistor includes an oxide semiconductor layer formed on a substrate and including a channel region, a source region and a drain region, a gate electrode insulated from the oxide semiconductor layer by a gate insulating film, and source electrode and drain electrode which are coupled to the source region and the drain region, respectively. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.

Claims

1. A thin film transistor, comprising:

a substrate;

an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region, the oxide semiconductor layer including a first layer portion and a second layer portion, the first layer portion having a first thickness and a first carrier concentration, the second layer portion having a second thickness and a second carrier concentration, each of the first carrier and the second carrier including an electron, the first layer and the second layer being made of the same material, the second carrier concentration being lower than the first carrier concentration;

a gate electrode insulated from the oxide semiconductor layer by a gate insulating film;

a source electrode coupled to the source region; and

a drain electrode coupled to the drain region.

2. The thin film transistor as claimed in claim 1, wherein the oxide semiconductor layer includes zinc oxide (ZnO).

3. The thin film transistor as claimed in claim 2, wherein the oxide semiconductor layer is doped with ions of gallium (Ga) or ions of indium (In).

4. The thin film transistor as claimed in claim 1, wherein the first thickness is 5 nm to 30 nm from the interface contacting the gate insulating film.

5. The thin film transistor as claimed in claim 1, wherein the first carrier concentration is 1×

10¹⁵ 1/cm³ to 1×

10¹⁷ 1/cm³, and the second carrier concentration is 1×

10¹² 1/cm³ to 1×

10¹⁵ 1/cm³.

6. The thin film transistor as claimed in claim 1, further comprising a passivation layer formed on the source electrode and the drain electrode.

7. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming a gate insulating film on the gate electrode;

forming an oxide semiconductor layer on the gate insulating film, the oxide semiconductor layer insulated from the gate electrode by the gate insulating film, the oxide semiconductor layer including a channel region, a source region, and a drain region, the step of forming the oxide semiconductor layer comprising;

depositing a first layer portion having a first thickness and a first carrier concentration, the first carrier including an electron; and

depositing a second layer portion having a second thickness and a second carrier concentration, the second carrier including an electron, the first layer and the second layer being made of the same material, the second carrier concentration being lower than the first carrier concentration;

forming a source electrode to be coupled to the source region; and

forming a drain electrode to be coupled to the drain region.

8. The method of manufacturing the thin film transistor as claimed in claim 7, the oxide semiconductor layer includes zinc oxide (ZnO).

9. The method of manufacturing the thin film transistor as claimed in claim 8, wherein the oxide semiconductor layer is doped with ions of gallium (Ga) or ions of indium (In).

10. The method of manufacturing the thin film transistor as claimed in claim 7, wherein the first thickness is 5 nm to 30 nm from the interface contacting the gate insulating film.

11. The method of manufacturing the thin film transistor as claimed in claim 7, wherein the first carrier concentration is 1×

10¹⁵ 1/cm³ to 1×

10¹⁷ 1/cm³, and the second carrier concentration is 1×

10¹² 1/cm³ to 1×

10¹⁵ 1/cm³.

12. The method of manufacturing the thin film transistor as claimed in claim 7, wherein the first carrier concentration and the second carrier concentration are controlled by an oxygen partial pressure.

13. The method of manufacturing the thin film transistor as claimed in claim 12, wherein the oxygen partial pressure is controlled in the range of 30% to 90%.

14. The method of manufacturing the thin film transistor as claimed in claim 7, further comprising forming a passivation layer on the source electrode and drain electrode.

15. A flat panel display device, comprising:

a first substrate comprising;

a first conductive line;

a second conductive line;

a thin film transistors coupled to the first conductive line and the second conductive line; and

a first electrode coupled to the thin film transistor, signals supplied to the first electrode being controlled by the thin film transistor;

a second substrate including a second electrode; and

a liquid crystal layer disposed between the first electrode and second electrode, the thin film transistor of the first substrate comprising;

a substrate;

an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region, the oxide semiconductor layer including a first layer portion and a second layer portion, the first layer portion having a first thickness and a first carrier concentration, the second layer portion having a second thickness and a second carrier concentration, each of the first carrier and the second carrier including an electron, the first layer and the second layer being made of the same material, the second carrier concentration being lower than the first carrier concentration;

a gate electrode insulated from the oxide semiconductor layer by a gate insulating film;

a source electrode coupled to the source region; and

a drain electrode coupled to the drain region.

16. The flat panel display device of claim 15, wherein the oxide semiconductor layer includes zinc oxide (ZnO).

17. The flat panel display device of claim 16, wherein the oxide semiconductor layer is doped with ions of gallium (Ga) or ions of indium (In).

18. The flat panel display device of claim 15, wherein the first thickness is 5 nm to 30 nm from the interface contacting the gate insulating film.

19. The flat panel display device of claim 15, wherein the first carrier concentration is 1×

10¹⁵ 1/cm³ to 1×

10¹⁷ 1/cm³, and the second carrier concentration is 1×

10¹² 1/cm³ to 1×

10¹⁵ 1/cm³.

20. A flat panel display device, comprising:

a first substrate comprising;

an organic light emitting device including a first electrode, an organic thin film layer, and a second electrode; and

a thin film transistor coupled to the organic light emitting device to control an operation of the organic light emitting device; and

a second substrate disposed facing the first substrate, the thin film transistor of the first substrate comprising;

a substrate;

an oxide semiconductor layer formed on the substrate and including a channel region, a source region and a drain region, the oxide semiconductor layer including a first layer portion and a second layer portion, the first layer portion having a first thickness and a first carrier concentration, the second layer portion having a second thickness and a second carrier concentration, each of the first carrier and the second carrier including an electron, the first layer and the second layer being made of the same material, the second carrier concentration being lower than the first carrier concentration;

a gate electrode insulated from the oxide semiconductor layer by a gate insulating film;

a source electrode coupled to the source region; and

a drain electrode coupled to the drain region.

21. The flat panel display device of claim 20, wherein the oxide semiconductor layer includes zinc oxide (ZnO).

22. The flat panel display device of claim 21, wherein the oxide semiconductor layer is doped with ions of gallium (Ga) or ions of indium (In).

23. The flat panel display device of claim 20, wherein the first thickness is 5 nm to 30 nm from the interface contacting the gate insulating film.

24. The flat panel display device of claim 20, wherein the first carrier concentration is 1×

10¹⁵ 1/cm³ to 1×

10¹⁷ 1/cm³, and the second carrier concentration is 1×

10¹² 1/cm³ to 1×

10¹⁵ 1/cm³.