Staggered column superjunction

• US 8,466,510 B2
• Filed: 10/30/2009
• Issued: 06/18/2013
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bobde, Madhur, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US12/610,052
• Publication Number:
  US 20110101446A1
• Time in Patent Office: 1,327 Days
• Field of Search: 257/335
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

Claims

1. A staggered column vertical superjunction semiconductor device comprising:

a cell region having one or more device cells, wherein a portion of the device cells in the active cell region include;

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of the first conductivity type located on top of the first semiconductor layer; and

a plurality of first doped columns formed in the second semiconductor layer to a first depth and a plurality of second doped columns formed in the second semiconductor layer to a second depth, wherein the first depth is greater than the second depth, wherein the first and second doped columns are doped with dopants of a same second conductivity type that is different from the first conductivity type and wherein the first and second doped columns extend along a portion of a thickness of the second semiconductor layer, wherein the first and second doped columns alternate with each other in a row, wherein depths of alternate first and second doped columns within the row alternate between deeper and shallower, and wherein the first and second columns are adjacent to portions of the second semiconductor layer of the first conductivity type.

2. The semiconductor device of claim 1 wherein the first and second doped columns are doped such that the columns of the first conductivity type are substantially horizontally charge balanced with the adjacent portions of the second semiconductor layer.

3. The semiconductor device of claim 1, wherein the first conductivity type is N-type.

4. The semiconductor device of claim 1, wherein the first conductivity type is P-type.

5. The semiconductor device of claim 1, wherein the second depth is approximately 5/6 or 6/7 of the first depth.

6. The semiconductor device of claim 1 further comprising termination regions, wherein the termination regions have one or more doped columns of the second conductivity type formed to the first depth in a second semiconductor layer of the first conductivity type.

7. The semiconductor device of claim 1 further comprising termination region, wherein the termination region includes doped columns of the second conductivity type, wherein all the doped columns of the second conductivity type in the termination region extend to the first depth.

8. The semiconductor device of claim 1 wherein the first column is deeper than the second column by about 5-15 microns.

9. The semiconductor device of claim 1, wherein all the doped columns of a second conductivity type in a corner of the active cell region extend to the first depth.

10. A vertical superjunction device comprising:

a plurality of columns of a second conductivity type alternating with one or more columns of a first conductivity type in a semiconductor substrate of the first conductivity type;

wherein one or more of the columns of the second conductivity type in a main portion of the device have a depth less than a depth of columns of the second conductivity type in a termination portion of the device, and wherein the columns of the second conductivity type are horizontally charge balanced with the columns of the first conductivity type.

11. A vertical superjunction device comprising:

a plurality of columns of a second conductivity type alternating with one or more columns of a first conductivity type;

wherein the columns of the second conductivity type are characterized by staggered depths,

wherein depths of alternate columns of the second conductivity type within a row of columns of the second conductivity type alternate between deeper and shallower, and wherein the columns of the second conductivity type are horizontally charge balanced with the columns of the first conductivity type.