Semiconductor device with enhanced mobility and method

• US 8,466,513 B2
• Filed: 06/13/2011
• Issued: 06/18/2013
• Est. Priority Date: 06/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M., Hossain, Zia, Huang, Kirk K., Padmanabhan, Balaji, Robb, Francine Y., Venkatraman, Prasad
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US13/159,255
• Publication Number:
  US 20120313161A1
• Time in Patent Office: 736 Days
• Field of Search: 438270-272, 257329-334
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having a major surface;

a trench control structure in the region of semiconductor material including a gate dielectric layer adjacent sidewall surfaces of the trench control structure and a gate electrode comprising a first conductive material overlying the gate dielectric layer, where the trench control structure further includes a shield electrode below the gate electrode, where the shield electrode is separated from the region of semiconductor material by a dielectric layer;

a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to form a channel region within the body region, where the channel region includes a source end and a drain end;

a source region within the body region having a first side adjacent the trench control structure and a second side opposite to the first side;

a first feature comprising a material other than the first conductive material within the gate electrode, where the first feature is configured to induce stress within portions of the channel region; and

a second feature within the shield electrode, where the second feature is configured to induce stress within a drift region of the semiconductor device.

2. The device of claim 1, where the first feature comprises a dielectric material.

3. The device of claim 1, where an edge of the first feature is placed within about 0.2 microns of the channel region.

4. The device of claim 1, where the first feature comprises two different materials, and where the first feature comprises a base portion in proximity to the drain end and a pair of pointed projections extending away from the base portion towards the major surface.

5. The device of claim 1, further comprising a third feature overlying the gate electrode and configured to induce stress in proximity to the source end of the channel.

6. The device of claim 1, where one of the first feature and the second feature comprises a composite structure.

7. The device of claim 1, where the second feature comprises a dielectric material.

8. The device of claim 1 further comprising a third feature adjoining the second side of the source, where the third feature is configured to induce stress in proximity to the source end of the channel region.

9. The device of claim 1 further comprising a second feature adjacent to opposing corners of the gate electrode in proximity to the drain end of the channel region and configured to induce stress within the drain end of the channel region.

10. The device of claim 1 further comprising a third feature adjoining the second side of the source, where the third feature is configured to induce stress in proximity to the source end of the channel region.

11. The device of claim 1 further comprising a third feature adjacent to opposing corners of the gate electrode in proximity to the drain end of the channel region and configured to induce stress within the drain end of the channel region.

12. An insulating gate field effect transistor structure having enhanced mobility comprising:

a region of semiconductor material having a first conductivity type, a first major surface, and a second major surface opposing the first major surface, where the region of semiconductor material at the second major surface is configured as a drain region;

a trench structure within the region of semiconductor material comprising a shield electrode in a lower portion of a trench, where the shield electrode is separated from the region of semiconductor material by a first dielectric layer, and a gate electrode in an upper portion of the trench, wherein the gate electrode is separated from the region of semiconductor material by a second dielectric layer and separated from the shield electrode by a third dielectric layer;

a body region having a second conductivity type opposite to the first conductivity type in the region of semiconductor material and adjacent to the trench structure, where the gate electrode is configured to form a channel region within the body region;

a source region of the first conductivity type in spaced relationship with the body region having a first side adjacent to the trench structure and a second side opposite to the first side;

a first region within the gate electrode and comprising a material configured to propagate stress within the region of semiconductor material adjacent to the trench control structure; and

a second region formed within the shield electrode and comprising a material configured to propagate stress within a drift region of the structure.

13. The structure of claim 12, where the first region comprises a dielectric material.

14. The structure of claim 13, where the first region comprises silicon nitride.

15. The structure of claim 12 further comprising a third region between the shield electrode and the gate electrode and comprising a material configured to propagates stress in proximity to a drain end of the channel region.

16. The structure of claim 12, where both the first and second regions comprise dielectric materials.

17. The structure of claim 12 further comprising a third region overlying the shield electrode and a fourth region overlying the gate electrode, where both the third and fourth regions comprise material configured to propagate stress within the region of semiconductor material adjacent to the trench structure.

18. The structure of claim 12 further comprising a third region adjacent to the second side of the source region and comprising a material configured to propagate stress in proximity to a source end of the channel region.

19. The structure of claim 18, where the third region comprises a dielectric material.

20. A method for forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a trench control structure in the region of semiconductor material including a shield electrode separated from the region of semiconductor material by a dielectric layer, a first feature formed within the shield electrode, a gate dielectric layer overlying sidewall surfaces of the trench control structure, a gate electrode comprising a first conductive material overlying the gate dielectric layer, and a second feature comprising a material other than the first conductive material within the gate electrode;

forming a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to form a channel region within the body region; and

forming a source region within the body region having a first side adjacent the trench control structure and a second side opposite to the first side, where the first feature is configured to induce stress within a drift region of the semiconductor device, and where the second feature is configured to induce stress within portions of the channel region.

21. The method of claim 20, where the step of forming the trench control structure includes forming the trench control structure where the second feature comprises a dielectric material.

22. The method of claim 21 further comprising the step of forming a third feature between the second feature and the channel region, where the third feature comprises a material different than the second feature and the first conductive material.

23. The method of claim 20, where the step of forming the trench control structure includes forming the trench control structure where an edge of the second feature is within about 0.2 microns of the channel region.

24. The method of claim 20, where the step of forming the trench control structure includes forming the trench control structure where the second feature comprises two different materials.

25. The method of claim 20 further comprising the step of forming a third feature overlying the gate electrode, where the third feature is configured to induce stress within portions of the channel regions.

26. The method of claim 20, where the step of forming the trench control structure comprises forming the trench control structure where the second feature comprises a plurality of spaced-apart stripe-like shapes.

27. The method of claim 20, where the step of forming the trench control structure comprises forming the trench control structure where the first feature comprises a plurality of spaced-apart stripe-like shapes.

28. The method of claim 20, where the step of forming the trench control structure comprises the steps of:

forming the gate dielectric layer adjacent side surfaces of a trench;

forming a conductive layer adjacent the gate dielectric layer;

forming the second feature adjacent the conductive layer; and

forming a conductive region adjacent the second feature and coupled to the conductive layer, where the conductive region and the conductive layer form the gate electrode.

29. The method of claim 28 further comprising the step of removing a portion of the conductive layer to form spacer layers.

30. The method of claim 28 further comprising the step of forming a layer of material between at least a portion the conductive layer and the second feature, where the layer of material is configured to induce stress within the channel region.

31. A method of forming a semiconductor device having enhanced mobility comprising the steps of:

providing a semiconductor material having a major surface and a drift region, where the device is configured as a vertical power semiconductor device;

forming a trench control structure in the region of semiconductor material including a gate dielectric layer overlying sidewall surfaces of the trench control structure and a gate electrode comprising a first conductive material overlying the gate dielectric layer;

forming a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to form a channel region within the body region;

forming a source region within the body region;

forming a contact trench extending within the source region to form first and second source region portions; and

forming a dielectric layer overlying exposed sidewall and lower surfaces of the contact trench, where the dielectric layer has thicker portions adjacent the sidewall surfaces, and where the thicker portions form dielectric features in spaced relationship with the semiconductor material, and where the dielectric features form stressed regions that propagate stress in proximity to the channel region.

32. The method of claim 31 further comprising the step of forming a feature within the gate electrode, where the feature comprises a material other than the first conductive material, and where the first feature is configured to induce stress within the channel region.

33. The method of claim 31 further comprising the steps of:

forming an enhancement region within the body region using the dielectric layer as a dopant mask;

removing the dielectric layer; and

forming a contact region within the contact trench.

34. The method of claim 31, where the step of forming the dielectric layer includes forming an oxide layer using wet oxidation at a temperature from between 825 degrees Celsius and 925 degrees Celsius.

35. A method of forming a semiconductor device having enhanced mobility comprising the steps of:

providing a semiconductor material having a major surface and a drift region, where the device is configured as a vertical power semiconductor device;

forming a hard mask layer overlying the major surface and having an opening;

forming a trench within the semiconductor material through the opening;

forming a gate dielectric layer overlying sidewalls of the trench;

forming a gate electrode recessed within the trench below the major surface, where the trench, gate dielectric layer and gate electrode are configured as a trench control structure;

oxidizing an upper portion of a sidewall of the trench using the hard mask layer as an oxidation mask to form a dielectric feature overlying a portion of the major surface adjacent the trench and below the hard mask layer;

forming a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to form a channel region within the body region, and where the dielectric feature forms a stressed region that propagates stress in proximity to the channel region;

forming a source region within the body region in proximity to the dielectric feature and the gate electrode;

forming a contact trench adjacent the source region, where the forming the contact trench step forms a sloped sidewalls along a portion of the source region; and

forming a contact layer within the contact trench.