Switch with reduced insertion loss

• US 8,466,736 B1
• Filed: 04/13/2012
• Issued: 06/18/2013
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Reynolds, Scott K.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cole, Brandon S
• Application Number:
  US13/446,115
• Publication Number:
  US 20130135051A1
• Time in Patent Office: 431 Days
• Field of Search: 327/403, 327/404, 327/427, 327/324, 327/426, 327/534, 327/537, 333/101, 333/103, 333/104, 333/262, 455/78
• US Class Current: 327/427
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.

Claims

1. A circuit comprising:

an amplifier having an input and an output; and

at least one transistor formed on at least one substrate, the at least one transistor comprising;

at least one terminal; and

at least a first well and a second well;

wherein the at least first and second wells are electrically isolated from the at least one substrate;

wherein the at least second well is electrically isolated from the at least first well;

wherein the second well is separated from the substrate by the first well;

wherein the input of the amplifier is electrically connected to the at least one terminal of the transistor; and

wherein the output of the amplifier is electrically connected to the at least first well of the at least one transistor, thereby biasing the first well with a signal proportional to a signal present at the at least one terminal of the transistor.

2. The circuit of claim 1, wherein the transistor is a component of a double-pull double-throw switch.

3. The circuit of claim 1, wherein the transistor is a component of an n-pull double-throw switch.

4. The circuit of claim 1, further comprising at least one coupling capacitor electrically connected between the input of the amplifier and the at least one terminal of the transistor.

5. The circuit of claim 1, further comprising at least one impedance-matching inductor electrically connected between the input of the amplifier and the at least one terminal of the transistor.

6. The circuit of claim 1, further comprising at least one coupling capacitor electrically connected between the output of the amplifier and the at least first well of the transistor.

7. The circuit of claim 1, further comprising at least one impedance-matching inductor electrically connected between the output of the amplifier and the at least first well of the transistor.

8. The circuit of claim 1, wherein the input of the amplifier has a significantly higher impedance than the output of the amplifier.

9. The circuit of claim 1, wherein the amplifier comprises a field effect transistor (FET).

10. The circuit of claim 1, wherein the amplifier is one of a source follower and an emitter follower.

11. The circuit of claim 1, wherein the at least one transistor comprises at least one triple-well field effect transistor.

12. The circuit of claim 1, wherein the at least one transistor comprises at least one positive field effect transistor.

13. The circuit of claim 1, wherein the at least one transistor comprises a plurality of wells, the plurality of wells comprising the at least one isolated first well.

14. A design structure embodied in a machine readable storage medium, the design structure comprising:

an amplifier having an input and an output; and

at least one transistor formed on at least one substrate, the at least one transistor comprising;

at least one terminal; and

at least a first well and a second well;

wherein the at least first and second wells are electrically isolated from the at least one substrate;

wherein the at least second well is electrically isolated from the at least first well;

wherein the second well is separated from the substrate by the first well;

wherein the input of the amplifier is electrically connected to the at least one terminal of the transistor; and

wherein the output of the amplifier is electrically connected to the at least first well of the at least one transistor, thereby biasing the first well with a signal proportional to a signal present at the at least one terminal of the transistor.

15. The design structure of claim 14 wherein the amplifier comprises a bipolar junction transistor (BJT).

16. The design structure of claim 14, wherein the transistor comprises at least one triple-well field effect transistor.

17. The design structure of claim 14, wherein the at least one transistor comprises a plurality of wells, the plurality of wells comprising the at least first well.