3D chip stack skew reduction with resonant clock and inductive coupling
First Claim
1. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata, the clock distribution network comprising:
- a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations;
wherein each of the plurality of clock distribution circuits comprises a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network, the resonant circuit including at least one capacitor and at least one inductor.
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Accused Products
Abstract
There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
62 Citations
20 Claims
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1. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata, the clock distribution network comprising:
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a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations; wherein each of the plurality of clock distribution circuits comprises a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network, the resonant circuit including at least one capacitor and at least one inductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata, the clock distribution network comprising:
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a plurality of clock grids, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations; a plurality of buffered clock trees, each being arranged on the respective one of the two or more strata for driving a respective one of the plurality of clock grids on a same one of the two or more strata and having at least a root and a plurality of clock buffers; a plurality of multiplexers, each being arranged on the respective one of the two or more strata, the plurality of multiplexers for providing a same single clock source to the root of each of the plurality of buffered clock trees, wherein each of the plurality of clock grids comprises at least one sector having a resonant circuit therein for providing stratum-to-stratum coupling for the clock distribution network. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification