Receiving circuit, LSI chip, and storage medium
First Claim
1. A receiving circuit comprising:
- a parallel circuit comprising at least two diode elements whose directions are opposite are electrically connected in parallel;
a coil whose one end is electrically connected in series with one end of the parallel circuit and the other end is connected to grounded;
a capacitor whose one end is electrically connected in series with the other end of the parallel circuit and the other end is connected to grounded; and
a comparison circuit for detecting voltage of a node to which the parallel circuit and the capacitor are electrically connected.
1 Assignment
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Accused Products
Abstract
A receiving circuit with a simple circuit structure for performing wireless communication utilizing electromagnetic induction is provided. An LSI chip and a storage medium where wireless communication utilizing electromagnetic induction is performed and the circuit scale and circuit size can be reduced are provided. The following receiving circuit may be used: a parallel circuit where two diode elements whose directions are opposite are connected in parallel is used, one end of the parallel circuit is connected to the other end of a coil whose one end is connected to a ground potential line, and a capacitor is connected in series with the other end of the parallel circuit. A transistor whose leakage current is markedly reduced may be used as a diode in the receiving circuit. Such a receiving circuit may be used in an LSI chip or a storage medium.
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Citations
5 Claims
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1. A receiving circuit comprising:
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a parallel circuit comprising at least two diode elements whose directions are opposite are electrically connected in parallel; a coil whose one end is electrically connected in series with one end of the parallel circuit and the other end is connected to grounded; a capacitor whose one end is electrically connected in series with the other end of the parallel circuit and the other end is connected to grounded; and a comparison circuit for detecting voltage of a node to which the parallel circuit and the capacitor are electrically connected. - View Dependent Claims (2, 3, 4, 5)
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Specification