Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a bit line;
m (m is a natural number of 3 or more) word lines;
a source line;
m signal lines;
first to m-th memory cells; and
a driver circuit,wherein each of the first to m-th memory cells comprises;
a first transistor including a first gate terminal, a first source terminal, and a first drain terminal;
a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and
a capacitor,wherein a channel of the second transistor includes an oxide semiconductor layer,wherein the source line is electrically connected to the first source terminal in the m-th memory cell,wherein a k-th (k is a natural number of 1 to m) signal line is electrically connected to the second gate terminal in the k-th memory cell,wherein a k-th word line is electrically connected to a first terminal of the capacitor in the k-th memory cell,wherein the second drain terminal in the j-th (j is a natural number of 3 to m) memory cell is electrically connected to the first gate terminal in the (j−
1)th memory cell, the second source terminal in the (j−
1)th memory cell, and a second terminal of the capacitor in the (j−
1)th memory cell,wherein the first gate terminal in the m-th memory cell, the second source terminal in the m-th memory cell, and a second terminal of the capacitor in the m-th memory cell are electrically connected to each other,wherein the first drain terminal in the j-th memory cell is electrically connected to the first source terminal in the (j−
1)th memory cell,wherein the driver circuit includes m first circuits and (m−
1) second circuits,wherein a write control signal and m row address selection signals are input to the driver circuit,wherein the write control signal and a j-th row address selection signal are input to a j-th first circuit,wherein an output from a (j−
2)th first circuit and an output from a (j−
1)th second circuit are input to a (j−
2)th second circuit,wherein the output from the (j−
1)th second circuit is input to a (j−
1)th signal line, andwherein an output from an m-th first circuit is input to an m-th signal line.
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Abstract
In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.
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Citations
11 Claims
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1. A semiconductor device comprising:
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a bit line; m (m is a natural number of 3 or more) word lines; a source line; m signal lines; first to m-th memory cells; and a driver circuit, wherein each of the first to m-th memory cells comprises; a first transistor including a first gate terminal, a first source terminal, and a first drain terminal; a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and a capacitor, wherein a channel of the second transistor includes an oxide semiconductor layer, wherein the source line is electrically connected to the first source terminal in the m-th memory cell, wherein a k-th (k is a natural number of 1 to m) signal line is electrically connected to the second gate terminal in the k-th memory cell, wherein a k-th word line is electrically connected to a first terminal of the capacitor in the k-th memory cell, wherein the second drain terminal in the j-th (j is a natural number of 3 to m) memory cell is electrically connected to the first gate terminal in the (j−
1)th memory cell, the second source terminal in the (j−
1)th memory cell, and a second terminal of the capacitor in the (j−
1)th memory cell,wherein the first gate terminal in the m-th memory cell, the second source terminal in the m-th memory cell, and a second terminal of the capacitor in the m-th memory cell are electrically connected to each other, wherein the first drain terminal in the j-th memory cell is electrically connected to the first source terminal in the (j−
1)th memory cell,wherein the driver circuit includes m first circuits and (m−
1) second circuits,wherein a write control signal and m row address selection signals are input to the driver circuit, wherein the write control signal and a j-th row address selection signal are input to a j-th first circuit, wherein an output from a (j−
2)th first circuit and an output from a (j−
1)th second circuit are input to a (j−
2)th second circuit,wherein the output from the (j−
1)th second circuit is input to a (j−
1)th signal line, andwherein an output from an m-th first circuit is input to an m-th signal line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification