Semiconductor device

• US 8,467,232 B2
• Filed: 07/29/2011
• Issued: 06/18/2013
• Est. Priority Date: 08/06/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori, Kato, Kiyoshi, Nagatsuka, Shuhei, Inoue, Hiroki
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Norman, James G
• Application Number:
  US13/193,966
• Publication Number:
  US 20120033485A1
• Time in Patent Office: 690 Days
• Field of Search: None
• US Class Current: 365/149
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.

Claims

1. A semiconductor device comprising:

a bit line;

m (m is a natural number of 3 or more) word lines;

a source line;

m signal lines;

first to m-th memory cells; and

a driver circuit,

wherein each of the first to m-th memory cells comprises;

a first transistor including a first gate terminal, a first source terminal, and a first drain terminal;

a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and

a capacitor,

wherein a channel of the second transistor includes an oxide semiconductor layer,

wherein the source line is electrically connected to the first source terminal in the m-th memory cell,

wherein a k-th (k is a natural number of 1 to m) signal line is electrically connected to the second gate terminal in the k-th memory cell,

wherein a k-th word line is electrically connected to a first terminal of the capacitor in the k-th memory cell,

wherein the second drain terminal in the j-th (j is a natural number of 3 to m) memory cell is electrically connected to the first gate terminal in the (j−

1)th memory cell, the second source terminal in the (j−

1)th memory cell, and a second terminal of the capacitor in the (j−

1)th memory cell,

wherein the first gate terminal in the m-th memory cell, the second source terminal in the m-th memory cell, and a second terminal of the capacitor in the m-th memory cell are electrically connected to each other,

wherein the first drain terminal in the j-th memory cell is electrically connected to the first source terminal in the (j−

1)th memory cell,

wherein the driver circuit includes m first circuits and (m−

1) second circuits,

wherein a write control signal and m row address selection signals are input to the driver circuit,

wherein the write control signal and a j-th row address selection signal are input to a j-th first circuit,

wherein an output from a (j−

2)th first circuit and an output from a (j−

1)th second circuit are input to a (j−

2)th second circuit,

wherein the output from the (j−

1)th second circuit is input to a (j−

1)th signal line, and

wherein an output from an m-th first circuit is input to an m-th signal line.

2. The semiconductor device according to claim 1,

wherein the driver circuit includes one delay circuit, and

wherein the output from the m-th first circuit is input to the m-th signal line though the delay circuit.

3. The semiconductor device according to claim 1,

wherein the driver circuit includes m delay circuits,

wherein the output from the (j−

1)th second circuit is input to the (j−

1)th signal line through a (j−

1)th delay circuit, and

wherein the output from the m-th first circuit is input to the m-th signal line though an m-th delay circuit.

4. The semiconductor device according to claim 1, wherein the first transistor includes:

a channel formation region provided over a substrate including a semiconductor material;

impurity regions provided so as to sandwich the channel formation region;

a first gate insulating layer over the channel formation region; and

a first gate electrode provided over the first gate insulating layer so as to overlap with the channel formation region.

5. The semiconductor device according to claim 4, wherein the substrate including a semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

6. The semiconductor device according to claim 4, wherein the semiconductor material is silicon.

7. The semiconductor device according to claim 1, wherein the second transistor includes a second gate electrode provided so as to overlap with the oxide semiconductor layer and a second gate insulating layer provided between the oxide semiconductor layer and the second gate electrode.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an oxide semiconductor material containing In, Ga, and Zn.

9. The semiconductor device according to claim 1, wherein the (m−

1) second circuits output “

1”

when at least one of the signals input is “

1”

.

10. The semiconductor device according to claim 1, wherein the first circuit is an AND circuit.

11. The semiconductor device according to claim 1, wherein the second circuit is an OR circuit.