nvSRAM with inverted recall

• US 8,467,243 B1
• Filed: 09/23/2010
• Issued: 06/18/2013
• Est. Priority Date: 09/28/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Shakeri, Kaveh, Ashokkumar, Jay
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Yang, Han
• Application Number:
  US12/888,737
• Time in Patent Office: 999 Days
• Field of Search: 365/185.08, 365/154, 365/189.15
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

A process of operating a memory circuit involves RECALLing a state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.

Claims

1. A process of operating a memory circuit comprising:

RECALLing a state of a volatile memory cell from a nonvolatile memory cell; and

inverting an output of the volatile memory cell after every other RECALL.

2. The process of operating a memory circuit of claim 1, wherein inverting an output of the volatile memory cell after every other RECALL further comprises:

inverting the output of the volatile cell after an odd number of RECALLs.

3. The process of operating a memory circuit of claim 1, further comprising:

RECALLing of the state of the volatile memory cell by pulling charge through the nonvolatile cell from a charge storage node of the volatile cell.

4. The process of operating a memory circuit of claim 3, wherein RECALLing of the state of the volatile memory cell by pulling charge through the nonvolatile cell from a charge storage node of the volatile cell further comprises:

RECALLing of the state of the volatile memory cell by pulling charge from exactly one charge storage node of the volatile cell through the nonvolatile cell.

5. The process of operating a memory circuit of claim 4, wherein RECALLing of the state of the volatile memory cell by pulling charge from exactly one charge storage node of the volatile cell through the nonvolatile cell further comprises:

RECALLing of the state of the volatile memory cell by pulling charge from a charge storage node of the volatile cell through exactly one trigate circuit of the nonvolatile cell.

6. The process of operating a memory circuit of claim 1, further comprising:

initializing the volatile cell to represent a logical one state; and

flipping the volatile cell state to represent a logical zero when the nonvolatile cell stores a logical one state for the volatile cell.

7. The process of operating a memory circuit of claim 1, further comprising:

initializing the volatile cell to represent an undetermined logical state; and

causing the volatile cell state to latch to a logical zero when the nonvolatile cell stores a logical one state for the volatile cell.

8. An nvRAM circuit comprising:

a volatile charge storage circuit and a nonvolatile charge storage circuit; and

logic to set, during every other RECALL, a logical state of the volatile charge storage circuit to the inverse of a logical state stored by the nonvolatile charge storage circuit.

9. The nvRAM circuit of claim 8, wherein the logic to set, during RECALL, a logical state of the volatile charge storage circuit to the inverse of a logical state stored by the nonvolatile charge storage circuit further comprises:

logic to pull down a TRUE charge storage node of the volatile charge storage circuit to a level representing a logical “

0”

when the nonvolatile charge storage circuit stores a state representing a logical “

1”

.

10. The nvRAM circuit of claim 8, the volatile charge storage circuit comprising a cross-coupled latch.

11. The nvRAM circuit of claim 10, the cross-coupled latch comprising two n-p transistor pairs.

12. The nvRAM circuit of claim 8, the nonvolatile charge storage circuit comprising a three transistor trigate.

13. The nvRAM circuit of claim 8, the nonvolatile charge storage circuit comprising exactly one trigate, the trigate comprising a silicon oxide nitride oxide SONOS transistor for nonvolatile charge storage.

14. The nvRAM circuit of claim 13, the exactly one trigate comprising three transistors in series, a first transistor of the trigate having a non-gate connection to a charge storage node of the volatile charge storage circuit, a second transistor of the trigate having a nongate connection to a power source, and a third transistor of the trigate being a nonvolatile charge storage device.

15. An nvRAM circuit comprising:

an SRAM cell coupled to a nonvolatile charge storage circuit, the nonvolatile charge storage circuit comprising exactly one nonvolatile charge storage transistor; and

logic to set, during RECALL, a logical state of the SRAM cell to the inverse of a logical state stored by the nonvolatile charge storage circuit, and to invert the output of the cell after every other RECALL.

16. The nvRAM circuit of claim 15, wherein the logic to set, during RECALL, a logical state of the SRAM cell to the inverse of a logical state stored by the nonvolatile charge storage circuit further comprises:

logic to pull down a TRUE charge storage node of the SRAM cell to a level representing a logical “

0”

when the nonvolatile charge storage circuit stores a state representing a logical “

1”

.

17. The nvRAM circuit of claim 15, the SRAM cell comprising a cross-coupled latch.

18. The nvRAM circuit of claim 17, the cross-coupled latch comprising two n-p transistor pairs.

19. The nvRAM circuit of claim 15, the nonvolatile charge storage circuit comprising a trigate.

20. The nvRAM circuit of claim 15, the nonvolatile charge storage circuit comprising exactly one trigate, the trigate comprising exactly one silicon oxide nitride oxide SONOS transistor for nonvolatile charge storage.