Implementing multipliers in a programmable integrated circuit device

• US 8,468,192 B1
• Filed: 03/03/2009
• Issued: 06/18/2013
• Est. Priority Date: 03/03/2009
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US12/396,766
• Time in Patent Office: 1,568 Days
• Field of Search: 708/492, 708/620, 708/625, 708627-632
• US Class Current: 708/620
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

The number of multipliers of a particular size that are required to perform a multiplication larger than that size is reduced. In the example of a 36-bit-by-36-bit multiplication, the number of 18-bit-by-18-bit multipliers required may be reduced from four to three. This may be achieved by using recursive decomposition techniques. As discussed in more detail below, if for each of two 36-bit numbers, the “digits” of each respective 36-bit number are added together, and then the two sums are multiplied, the resulting term can be combined additively with the product of the least-significant group of bits of the two 36-bit numbers and the product of the most-significant group of bits of the two 36-bit numbers to provide the desired product. A specialized processing block includes structures to facilitate the recursive decomposition technique.

Claims

1. A method of configuring a programmable integrated circuit device to perform a multiplication operation on a number of multiplicand input values each having a first plurality of bits, wherein:

said programmable integrated circuit device incorporates multiplier circuits for multiplicand input values each having a second plurality of bits,

said multiplier circuits are grouped into specialized processing blocks,

each of said specialized processing blocks comprises only two of said multiplier circuits, and further comprises combinatorial circuitry for combining outputs of said two of said multiplier circuits, and

said programmable integrated circuit device further comprises interconnection conductors for selectably connecting output of at least one multiplier circuit in a first one of said specialized processing blocks to said combinatorial circuitry in at least a second one of said specialized processing blocks;

said method comprising;

configuring logic of said programmable integrated circuit device to break up each of said multiplicand input values into a plurality of segments, each segment having said second plurality of bits, a first one of said segments of one of said multiplicand input values being of greater significance than a second one of said segments of said one of said multiplicand input values, said second one of said segments being of lesser significance;

configuring logic of said programmable integrated circuit device for adding together, for each of said multiplicand input values, said segments of greater significance and lesser significance, to create a respective sum for each of said multiplicand values;

configuring logic of said programmable integrated circuit device for multiplying together said segments of greater significance using a first one of said multiplier circuits, for multiplying together said segments of lesser significance using a second one of said multiplier circuits, and for multiplying together said sums using a third one of said multiplier circuits, said configuring logic of said programmable integrated circuit device for multiplying comprises configuring said interconnection conductors to connect output of at least one multiplier circuit in said first one of said specialized processing blocks to said combinatorial circuitry in said at least a second one of said specialized processing blocks; and

configuring logic of said programmable integrated circuit device to shift outputs of said first and second ones of multiplier circuits by respective amounts and to combine outputs of said first, second and third ones of said multiplier circuits according to a recursive decomposition of said multiplication operation.

2. The method of claim 1 wherein said recursive decomposition is a Karatsuba decomposition.

3. The method of claim 1 wherein:

said programmable integrated circuit device further includes input adder circuits; and

said configuring logic of said programmable integrated circuit device for adding comprises;

routing said segments to at least one of said input adder circuits, and

routing output of said at least one of said input adder circuits to at least one input of said multiplier circuits.

4. A programmable integrated circuit device configured to perform a multiplication operation on a number of multiplicand input values each having a first plurality of bits, wherein:

said programmable integrated circuit device incorporates multiplier circuits for multiplicand input values each having a second plurality of bits,

said multiplier circuits are grouped into specialized processing blocks,

each of said specialized processing blocks comprises only two of said multiplier circuits, and further comprises combinatorial circuitry for combining outputs of said two of said multiplier circuits, and

said programmable integrated circuit device further comprises configurable interconnection conductors configured to connect output of at least one multiplier circuit in a first one of said specialized processing blocks to said combinatorial circuitry in at least a second one of said specialized processing blocks, said configured programmable logic device comprising;

logic configured to break up each of said multiplicand input values into a plurality of segments, each segment having said second plurality of bits, a first one of said segments of one of said multiplicand input values being of greater significance than a second one of said segments of said one of said multiplicand input values, said second one of said segments being of lesser significance;

logic configured for adding together, for each of said multiplicand input values, said segments of greater significance and lesser significance, to create a respective sum for each of said multiplicand values;

logic configured for multiplying together said segments of greater significance using a first one of said multiplier circuits, multiplying together said segments of lesser significance using a second one of said multiplier circuits, and multiplying together said sums using a third one of said multiplier circuits; and

logic configured to shift outputs of said first and second ones of multiplier circuits by respective amounts and to combine outputs of said first, second and third ones of said multiplier circuits according to a recursive decomposition of said multiplication operation.

5. The programmable integrated circuit device of claim 4 wherein said recursive decomposition is a Karatsuba decomposition.

6. The programmable integrated circuit device of claim 4 further comprising:

input adder circuits;

wherein;

said logic configured for adding comprises;

configurable routing configured to connect said segments to at least one of said input adder circuits, and to route output of said at least one of said input adder circuits to at least one input of said multiplier circuits.

7. The programmable integrated circuit device of claim 4 wherein said at least a second one of said specialized processing blocks comprises ones of said specialized processing blocks adjacent to both sides of said first one of said specialized processing blocks.

8. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform a multiplication operation on a number of multiplicand input values each having a first plurality of bits, wherein:

said programmable integrated circuit device incorporates multiplier circuits for multiplicand input values each having a second plurality of bits,

said multiplier circuits are grouped into specialized processing blocks,

each of said specialized processing blocks comprises only two of said multiplier circuits, and further comprises combinatorial circuitry for combining outputs of said two of said multiplier circuits, and

said programmable integrated circuit device further comprises interconnection conductors for selectably connecting output of at least one multiplier circuit in a first one of said specialized processing blocks to said combinatorial circuitry in at least a second one of said specialized processing blocks, said instructions comprising;

instructions to configure logic of said programmable integrated circuit device to break up each of said multiplicand input values into a plurality of segments, each segment having said second plurality of bits, a first one of said segments of one of said multiplicand input values being of greater significance than a second one of said segments of said one of said multiplicand input values, said second one of said segments being of lesser significance;

instructions to configure logic of said programmable integrated circuit device for adding together, for each of said multiplicand input values, said segments of greater significance and lesser significance, to create a respective sum for each of said multiplicand values;

instructions to configure logic of said programmable integrated circuit device for multiplying together said segments of greater significance using a first one of said multiplier circuits, for multiplying together said segments of lesser significance using a second one of said multiplier circuits, and for multiplying together said sums using a third one of said multiplier circuits, said instructions to configure logic of said programmable integrated circuit device for multiplying comprise instructions to configure said interconnection conductors to connect output of at least one multiplier circuit in said first one of said specialized processing blocks to said combinatorial circuitry in said at least a second one of said specialized processing blocks; and

instructions to configure logic of said programmable integrated circuit device to shift outputs of said first and second ones of multiplier circuits by respective amounts and to combine outputs of said first, second and third ones of said multiplier circuits according to a recursive decomposition of said multiplication operation.

9. The non-transitory machine-readable data storage medium of claim 8 wherein said recursive decomposition is a Karatsuba decomposition.

10. The non-transitory machine-readable data storage medium of claim 8 wherein:

said programmable integrated circuit device further includes input adder circuits; and

said instructions to configure logic of said programmable integrated circuit device for adding comprise;

instructions to configure routing of said segments to at least one of said input adder circuits, and

instructions to configure routing output of said at least one of said input adder circuits to at least one input of said multiplier circuits.