Dual thread processor

• US 8,468,324 B2
• Filed: 05/31/2012
• Issued: 06/18/2013
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Chen, Hong-Yi, Sutardja, Sehat
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US13/485,642
• Publication Number:
  US 20120239908A1
• Time in Patent Office: 383 Days
• Field of Search: None
• US Class Current: 712/205
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time. The processor causes data associated with the first processor thread to pass through the processor'"'"'s pipeline during the first periods of processor time. A second counter is similarly configured. The processor can be configured to receive an input defining processor time to be allocated to one or more processor threads and to use the input to change one or more of the counters such that subsequent periods of processor times for the one or more processor threads are affected.

Claims

1. A processor, comprising:

a first pipeline stage;

a second pipeline stage;

a first selector configured to provide data to the first pipeline stage;

a first input register configured to provide data to the first selector;

a second input register configured to provide data to the first selector;

a second selector configured to receive data output of the first pipeline stage;

a first output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage;

a second output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage;

a first thread allocation counter configured to store a first processor time allocation that controls first periods of processor time for a first processor thread such that the first processor thread fully uses each of the first periods of processor time, wherein the first processor time allocation exclusively provides equal amounts of processor time to the first processor thread in each of the first periods, wherein the processor is configured to cause data associated with the first processor thread to pass through the first input register, the first pipeline stage, the first output register, and the second pipeline stage during the first periods of processor time;

a second thread allocation counter configured to store a second processor time allocation that controls second periods of processor time for a second processor thread such that the second processor thread fully uses each of the second periods of processor time, wherein the second processor time allocation exclusively provides equal amounts of processor time to the second processor thread in each of the second periods, wherein the processor is configured to cause data associated with the second processor thread to pass through the second input register, the first pipeline stage, the second output register, and the second pipeline stage during the second periods of processor time; and

circuitry configured to receive an input defining processor time to be allocated to the first processor thread, the second processor thread, or both, and to use the input to change the first, second, or both thread allocation counters such that subsequent periods of processor times for the first, second, or both processor threads are affected.

2. The processor of claim 1, wherein the input is provided by a user via a graphical user interface.

3. The processor of claim 1, wherein the input is generated by a software program.

4. The processor of claim 1, wherein the first selector includes a multiplexer, and wherein the second selector includes a de-multiplexer.

5. The processor of claim 1, wherein the first pipeline stage includes one of an instruction fetch unit, decode logic, issue logic, or execution unit.

6. The processor of claim 1, further comprising:

a first register file including one or more banks operable to store data associated with the first processor thread; and

a second register file including one or more banks operable to store data associated with the second processor thread.

7. The processor of claim 1, further comprising:

a first program counter operable to indicate an execution status of the first processor thread; and

a second program counter operable to indicate an execution status of the second processor thread.

8. A system comprising:

a memory to store instructions for a first processor thread, and to store instructions for a second processor thread; and

a processor comprising a first pipeline stage, a second pipeline stage, a first selector configured to provide data to the first pipeline stage, a first input register configured to provide data to the first selector, a second input register configured to provide data to the first selector, a second selector configured to receive data output of the first pipeline stage, a first output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage, and a second output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage,

wherein the processor further comprises a first thread allocation counter configured to store a first processor time allocation that controls first periods of processor time for the first processor thread such that the first processor thread fully uses each of the first periods of processor time, wherein the first processor time allocation exclusively provides equal amounts of processor time to the first processor thread in each of the first periods, wherein the processor is configured to cause data associated with the first processor thread to pass through the first input register, the first pipeline stage, the first output register, and the second pipeline stage during the first periods of processor time,

wherein the processor further comprises a second thread allocation counter configured to store a second processor time allocation that controls second periods of processor time for the second processor thread such that the second processor thread fully uses each of the second periods of processor time, wherein the second processor time allocation exclusively provides equal amounts of processor time to the second processor thread in each of the second periods, wherein the processor is configured to cause data associated with the second processor thread to pass through the second input register, the first pipeline stage, the second output register, and the second pipeline stage during the second periods of processor time, and

wherein the processor is configured to receive an input defining processor time to be allocated to the first processor thread, the second processor thread, or both, and to use the input to change the first, second, or both thread allocation counters such that subsequent periods of processor times for the first, second, or both processor threads are affected.

9. The system of claim 8, wherein the input is provided by a user via a graphical user interface.

10. The system of claim 8, wherein the input is generated by a software program.

11. The system of claim 8, wherein the first selector includes a multiplexer, and wherein the second selector includes a de-multiplexer.

12. The system of claim 8, wherein the first pipeline stage includes one of an instruction fetch unit, decode logic, issue logic, or execution unit.

13. The system of claim 8, further comprising:

a first register file including one or more banks operable to store data associated with the first processor thread; and

a second register file including one or more banks operable to store data associated with the second processor thread.

14. The system of claim 8, further comprising:

a first program counter operable to indicate an execution status of the first processor thread; and

a second program counter operable to indicate an execution status of the second processor thread.

15. A method, comprising:

loading two or more processor time allocations for respective two or more processor threads in a processor, the two or more processor time allocations exclusively providing processor time to the respective two or more processor threads, wherein the two or more processor time allocations are fully used by the respective two or more processor threads, wherein storing the two or more processor time allocations comprises writing values into two or more hardware allocation counters of the processor based on received input, wherein the values determine a weighting that corresponds to processor time allocated to the two or more processor threads, which correspond to the two or more hardware allocation counters;

retrieving and executing instructions of the two or more processor threads in a pipeline of the processor in accordance with two or more program counters, which correspond to the two or more processor threads, wherein the retrieving and executing is performed separately for respective ones of the two or more processor threads; and

performing a context switch automatically, based on an output of at least one of the two or more hardware allocation counters, between the separate retrieving and executing of instructions of the two or more processor threads according to the allocated processor time.

16. The method of claim 15, wherein the input is received from a user.

17. The method of claim 16, wherein the user retains full control of processor time allotment rather than relinquishing control to an operating system.

18. The method of claim 16, wherein the input defines portions of processor time to be allocated to the two or more processor threads.

19. The method of claim 15, wherein the loading occurs dynamically during program execution.

20. The method of claim 19, wherein the input is received from a software application.

21. The method of claim 15, wherein the context switch is performed at an end of an instruction cycle after data from a pipeline stage has been saved to an associated register.