Pipeline configuration protocol and configuration unit communication

• US 8,468,329 B2
• Filed: 06/08/2012
• Issued: 06/18/2013
• Est. Priority Date: 02/25/1999
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Armin Nuckel
• Inventors: Vorbach, Martin, Baumgarte, Volker, Ehlers, Gerd, May, Frank, Nckel, Armin
• Primary Examiner(s): Elamin, M
• Application Number:
  US13/491,894
• Publication Number:
  US 20120311301A1
• Time in Patent Office: 375 Days
• Field of Search: 713/1, 713/2, 713/100, 714/38.1, 717/129
• US Class Current: 713/1
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.

Claims

1. A method of synchronizing data processing of a hardware processor arrangement on an integrated module that includes a plurality of data processing units, the method comprising:

for each of at least one barrier included in a program sequence, during execution of the program;

responsive to reaching the respective barrier, determining, by the processor arrangement, whether all instructions preceding the respective barrier have been successfully scheduled for execution; and

continuing, by the processor arrangement, execution of the program beyond the respective barrier in accordance with the determination;

wherein the processor arrangement is adapted for the continuing to include, if a result of the determination is that at least one of the instructions preceding the respective barrier has not been successfully scheduled for execution, initially stopping the program execution until all of the instructions preceding the respective barrier have been successfully scheduled for execution.

3. The method of claim 1, wherein the instructions preceding the respective barrier include instructions for at least one arithmetic logic unit.

4. The method of claim 3, wherein the hardware processor arrangement includes multiple processors.

5. The method of claim 4, wherein the barrier ensures that instructions are executed in correct order.

6. The method of claim 5, wherein the barrier is implemented by a token.

7. The method of claim 5, wherein the barrier ensures that all instructions behind the barrier are executed in order.

8. The method of claim 1, wherein the hardware processor arrangement includes multiple processors.

9. The method of claim 8, wherein the barrier ensures that instructions are executed in correct order.

10. The method of claim 9, wherein the barrier ensures that all instructions behind the barrier are executed in correct order.

11. The method of claim 8, wherein the barrier is formed by a token.

12. The method of claim 1, wherein the barrier ensures that all instructions behind the barrier are executed in order.

13. The method of claim 12, wherein the barrier ensures that all instructions behind the barrier are executed in correct order.

14. The method of claim 12, wherein the barrier is formed by a token.

15. The method of claim 1, wherein the barrier is formed by a token.

2. A method of synchronizing data processing of a hardware processor arrangement on an integrated module that includes a plurality of data processing units, the method comprising:

responsive to reaching, during execution of a program, a barrier included in the program sequence, halting, by the processor arrangement, the execution of the program until the processor arrangement determines that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.

16. The method of claim 2, wherein the instructions preceding the respective barrier include instructions for at least one arithmetic logic unit.

17. The method of claim 16, wherein the hardware processor arrangement includes multiple processors.

18. The method of claim 17, wherein the barrier ensures that instructions are executed in correct order.

19. The method of claim 18, wherein the barrier is implemented by a token.

20. The method of claim 17, wherein the barrier ensures that all instructions behind the barrier are executed in order.

21. The method of claim 2, wherein the hardware processor arrangement includes multiple processors.

22. The method of claim 21, wherein the barrier ensures that instructions are executed in correct order.

23. The method of claim 22, wherein the barrier ensures that all instructions behind the barrier are executed in correct order.

24. The method of claim 21, wherein the barrier is formed by a token.

25. The method of claim 2, wherein the barrier ensures that all instructions behind the barrier are executed in order.

26. The method of claim 25, wherein the barrier ensures that all instructions behind the barrier are executed in correct order.

27. The method of claim 25, wherein the barrier is formed by a token.

28. The method of claim 2, wherein the barrier is formed by a token.