Layout method for soft-error hard electronics, and radiation hardened logic cell

• US 8,468,484 B2
• Filed: 03/20/2012
• Issued: 06/18/2013
• Est. Priority Date: 01/17/2008
• Status: Active Grant

• Current Assignee: RCI Europe AB
• Original Assignee: Klas Olof Lilja
• Inventors: Lilja, Klas Olof
• Primary Examiner(s): TAT, BINH C
• Application Number:
  US13/425,231
• Publication Number:
  US 20120180005A1
• Time in Patent Office: 455 Days
• Field of Search: 716118-125
• US Class Current: 716/119
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Claims

1. A method of designing a circuit layout of an electronic integrated circuit, the circuit comprising component contact areas, voltage states, and nets, the method being embodied in a data processing apparatus having at least an arithmetic processor and memory, the method comprising the steps of:

a. determining the effect on the voltage state of one or more nets in the circuit, due to a single event occurring near each contact area, for each contact area in the circuit;

b. categorizing the contact areas in such a way that contact areas for which a single event have opposing effects on the voltage state of the nets in the circuit, and for which a single event has a non-opposing effect on the voltage state of the nets in the circuit, are identified;

c. placing these contact areas in such a way that when a single event has opposing effects on the voltage state of the circuit nets, the opposing first and second contact areas are placed as close to each other as permitted by the circuit and by the design rules;

d. placing a first contact area and a second contact area, with non-opposing effects on the voltage state of the nets in the circuit, said non-opposing effects caused by a single event, wherein the first and second contact areas are non-adjoining, and placing a third contact area in between the first and second contact areas, wherein said third contact area has an effect on the voltage state of the nets in the circuit opposing those of the first and second contact areas, and wherein the third contact area'"'"'s effect on the voltage state of the nets in the circuit is caused by a single event;

e. adjusting the contact areas so that the opposing effects of a single event are of approximately equal magnitude, to substantially minimize the effect of the single event on the voltage state of the nets in the circuit;

f. designing a mask layout of the integrated circuit, the mask layout based on the circuit layout designed using this method; and

g. storing the mask layout in the data processing apparatus memory.

2. The method of designing a circuit layout of an electronic integrated circuit of claim 1, further comprising a non-transitory computer-readable medium storing a computer program for causing a computer to perform at least one of the steps in the method.

3. The method of claim 1, wherein the circuit has at least two nets carrying the same signal (or the signal and its inverse), where each of these nets have at least two contact areas for which a single event has an opposing effect on the voltage state of said two nets, comprising:

a. placing a first contact area and a second contact area, each from a separate redundant net, for which a single event has the effect of changing the voltage state on the two redundant nets, wherein the first and second contact areas are non-adjoining, and placing a third contact area in between the first and second contact areas, said third contact area having an effect on the voltage state on at least one of the redundant nets, and wherein said effect of the third contact area is caused by a single event and opposes the effects of the first and second contact areas; and

b. adjusting the strength of the effect of a single event on the placed contact areas in such a way that any single event that affects (passes through) the two redundant nets, at maximum can change the state of one of the nets, but never both nets.

4. The method of claim 1 or 2, wherein the circuit utilizes MOSFET devices, further comprising:

a. identifying all MOSFET source (S) and drain (D) doping areas, which are not directly connected to the power-nets (VSS, VDD) as the contact areas of claims 1) and (2); and

b. identifying the n-type MOSFET drains or sources, as contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, low, and the p-type MOSFET drains or sources, as contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, high.

5. The method of claim 3, further comprising:

a. adding additional MOSFET devices between two nets, which at any time, carry opposite voltage states (high/low voltage level), in such a way that if one (first) of the nets is affected by a single event, such that its'"'"' voltage state is changed, then the additional MOSFET device turns on, connecting the two nets, and hence ensures that the state of the second net is not changed; and

b. connecting the sources or drains of the p-type MOSFETs in the two nets by additional p-type MOSFETs with their gates connected to the high level power net (VDD), and connecting the sources or drains of the n-type MOSFETs in the two nets by additional n-type MOSFETs with their gates connected to the low level power net (VSS).

6. The method of claim 1, wherein the adjustment of the contact areas in the layout of the integrated circuit comprises adjusting at least one of the following:

the size, the area, and the adjacency of the contact areas to other structures in the layout of the integrated circuit.