Concurrent thread execution using user-level asynchronous signaling

• US 8,468,526 B2
• Filed: 06/30/2006
• Issued: 06/18/2013
• Est. Priority Date: 06/30/2006
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Saha, Bratin, Adl-Tabatabai, Ali-Reza, Jacobson, Quinn A.
• Primary Examiner(s): An, Meng
• Assistant Examiner(s): WAI, ERIC CHARLES
• Application Number:
  US11/480,090
• Publication Number:
  US 20080005737A1
• Time in Patent Office: 2,545 Days
• Field of Search: None
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

Various usage models are provided to utilize a Monitor and Call (“mcall”) instruction that incorporates user-level asynchronous signaling. The various usage models utilize the mcall instruction in a multithreading system in order to enhance concurrent thread execution. Other embodiments are also described and claimed.

Claims

1. A system for detecting a conflict, comprising:

a first thread unit and a second thread unit, the first and second thread unit to execute two concurrent threads of a software application;

a memory coupled to the first and second thread units;

said memory to store software instructions to implement an atomic multiple-compare and single-swap (“

kcss”

) operation, wherein the kcss operation includes a call to an mcall instruction and is to monitor access to k addresses organized as an array, wherein the kcss operation is to detect, by the first thread unit, a conflict between the two concurrent threads based on detecting a write by the second thread unit to one of the k addresses in the array and is to utilize a hardware mechanism of the first thread unit to trigger a user code handler responsive to said conflict;

the hardware mechanism of the first thread unit to perform an asynchronous control transfer to the user code handler responsive to the write, by the second thread unit, to the one of the k addresses in the array;

wherein said user code handler includes one or more instructions to determine whether the conflict occurred before an atomic compare-and-swap of a kth address specified in the kcss operation.

2. The system of claim 1, wherein:

said memory is a DRAM.

3. The system of claim 1, wherein:

said software instructions include instructions for a software transactional memory transaction abort operation.

4. The system of claim 3, wherein:

said software instructions are further to detect a write operation, by the second thread unit, to an input data address for an atomic software transaction being executed by the first thread unit.

5. The system of claim 1, wherein:

said software instructions include instructions for a priority inversion correction operation.

6. The system of claim 5, wherein:

said software instructions are further to detect a write operation, by the second thread unit, to an inversion indicator monitored by the first thread unit.

7. The system of claim 6, wherein:

said software instructions are further to stall execution of the first thread unit and release a software lock held by the first thread unit.

8. A method, comprising:

enabling monitoring of one or more memory locations responsive to execution of an atomic multiple-compare and single-swap (“

kcss”

) operation by a first thread unit, the one or more memory locations corresponding to a software transaction descriptor record for a transaction;

wherein the kcss operation includes a call to an mcall instruction and is to monitor access to the one or more memory locations organized as an array;

beginning to execute a set of one or more instructions associated with the transaction on a first thread unit;

responsive to a write operation to the at least one of the one or more memory locations by a second thread unit, disrupting the execution of the set of instructions on the first thread unit, due to the execution of the kcss instruction, and transferring control to user-level handler code to be executed by the first thread unit;

wherein said disrupting is performed by asynchronous user-level signaling hardware;

and wherein the user-level handler code is to abort the transaction and cause a false value to be returned for the transaction.

9. The method of claim 8, wherein:

said user-level handler code is to return a failure indication if said kcss operation was not successfully completed before said disruption.

10. The method of claim 8, wherein:

the set of one or more instructions is a first thread.

11. The method of claim 10, wherein:

said write operation is performed by a second thread, the second thread having higher priority than the first thread.

12. The method of claim 11, wherein:

said user-level handler code is further to release a lock held by the first thread.

13. The method of claim 8, wherein:

wherein said transferring is performed without a change in privilege level for the first thread unit.

14. An article comprising:

a non-transitory computer storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a first thread unit, the instructions provide for;

enabling monitoring of one or more memory locations associated with an atomic multiple-compare and single-swap (“

kcss”

) operation, wherein the kcss operation includes a call to an mcall instruction and is to monitor access to the one or more memory locations organized as an array;

beginning to perform a set of one or more instructions associated with the kcss operation on the first thread unit;

responsive to a write operation to at least one of the one or more the memory locations by a second thread unit, disrupting the execution of the set of instructions on the first thread unit, due to execution of the kcss instruction, and transferring control to user-level handler code to be executed by the first thread unit;

wherein said disrupting is performed by asynchronous user-level signaling hardware; and

wherein said user-level handler code is to perform one or more actions associated with abort of the kcss operation.

15. The article of claim 14, wherein:

said user-level handler code is to return a failure indication responsive to a memory modification by the second thread unit to at least one of the one or more memory locations that breaks atomicity for the software transaction.

16. The article of claim 14, wherein:

said user-level handler code is to return a failure indication if said kcss operation was not successfully completed before said disruption.

17. The article of claim 14, wherein:

the set of one or more instructions is a first thread.

18. The article of claim 17, wherein:

said write operation is performed by a second thread, the second thread having higher priority than the first thread.

19. The article of claim 18, wherein:

said user-level handler code is further to release a lock held by the first thread.

20. The article of claim 14, wherein:

wherein said transferring is performed without a change in privilege level for the first thread unit.