Vital solid state controller
First Claim
Patent Images
1. A signal processing device comprising a first processing apparatus having a first processing apparatus output and a second processing apparatus having a second processing apparatus output:
- the first processing apparatus configured to perform a first process on an input signal set independent of the second processing apparatus to generate a first processing apparatus output signal, wherein the input signal set comprises one or more input signals;
the second processing apparatus configured to perform the first process on the input signal set independent of the first processing apparatus to generate a second processing apparatus output signal;
wherein a first processing apparatus failure signal is provided at the first processing apparatus output when the first processing apparatus fails integrity testing;
further wherein the first processing apparatus output signal is provided at the first processing apparatus output when the first processing apparatus passes integrity testing;
further wherein a second processing apparatus failure signal is provided at the second processing apparatus output when the second processing apparatus fails integrity testing;
further wherein the second processing apparatus output signal is provided at the second processing apparatus output when the second processing apparatus passes integrity testing;
wherein the first processing apparatus output and the second processing apparatus output are independent and are configured to provide processing apparatus output signals to be combined to generate a signal processing device output signal.
1 Assignment
0 Petitions
Accused Products
Abstract
A vital programmable logic device (VPD) is provided having at least two microprocessors. The VPD is configured to provide failsafe operation of a vital control system while operating in a closed circuit environment. In at least one embodiment of the present invention, railroad grade crossing signals are controlled by the VPD.
99 Citations
23 Claims
-
1. A signal processing device comprising a first processing apparatus having a first processing apparatus output and a second processing apparatus having a second processing apparatus output:
-
the first processing apparatus configured to perform a first process on an input signal set independent of the second processing apparatus to generate a first processing apparatus output signal, wherein the input signal set comprises one or more input signals; the second processing apparatus configured to perform the first process on the input signal set independent of the first processing apparatus to generate a second processing apparatus output signal; wherein a first processing apparatus failure signal is provided at the first processing apparatus output when the first processing apparatus fails integrity testing; further wherein the first processing apparatus output signal is provided at the first processing apparatus output when the first processing apparatus passes integrity testing; further wherein a second processing apparatus failure signal is provided at the second processing apparatus output when the second processing apparatus fails integrity testing; further wherein the second processing apparatus output signal is provided at the second processing apparatus output when the second processing apparatus passes integrity testing; wherein the first processing apparatus output and the second processing apparatus output are independent and are configured to provide processing apparatus output signals to be combined to generate a signal processing device output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A signal processing device for processing an input signal set comprising one or more input signals, the signal processing device comprising:
-
a first controller comprising a first microprocessor configured to execute application program logic and coupled to a first relay circuit driver, the first microprocessor comprising a first controller input configured to receive the input signal set, and the first relay circuit driver configured to generate the following; a first controller output signal at a first controller output when the first microprocessor passes integrity testing; a first controller failure signal at the first controller output when the first microprocessor fails integrity testing; a second controller comprising a second microprocessor configured to execute application program logic and coupled to a second relay circuit driver, the second microprocessor comprising a second controller input configured to receive the input signal set, and the second relay circuit driver configured to generate the following; a second controller output signal at a second controller output when the second microprocessor passes integrity testing; a second controller failure signal at the second controller output when the second microprocessor fails integrity testing; wherein generation of the first controller output signal is independent of generation of the second controller output signal; and further wherein the application program logic of the first microprocessor is the same as the application program logic of the second microprocessor. - View Dependent Claims (10, 11, 12, 13)
-
- 14. A signal processing device comprising first and second processing apparatus that are separate and independent from one another in their processing of an input signal set, each of the first and second processing apparatus having a dedicated and independent output configured to provide a complementary output control signal when each processing apparatus passes integrity testing, wherein integrity testing comprises a health check protocol performed on each of the first and second processing apparatus, wherein the health check protocol is independent of the processing of the input signal set.
-
18. A signal processing device comprising:
-
a first signal processing apparatus comprising a first controller, the first signal processing apparatus configured to generate a first control signal by performing a logic process using an input signal set comprising one or more input signals; a second signal processing apparatus comprising a second controller, the second signal processing apparatus configured to generate a second control signal by performing the logic process using the input signal set; health check apparatus configured to perform integrity testing of the first and second controllers; wherein the first signal processing apparatus generates the first control signal independent of the second signal processing apparatus and further wherein the second signal processing apparatus generates the second control signal independent of the first signal processing apparatus; further wherein, when the first and second controllers both pass integrity testing, and when there is no component failure within the signal processing device, the first and second control signals control an output device coupled to the first and second signal processing apparatus. - View Dependent Claims (19, 20)
-
-
21. A signal processing device comprising:
-
a first signal processing apparatus comprising a first controller, the first signal processing apparatus configured to generate a first controller output signal by performing a logic process using an input signal set comprising one or more input signals; a second signal processing apparatus comprising a second controller, the second signal processing apparatus configured to generate a second controller output signal by performing the logic process using the input signal set; health check apparatus configured to perform integrity testing of the first and second controllers; wherein, when the first and second controllers both pass integrity testing, and when there is no component failure within the signal processing device, the first and second controller output signals are based on the logic process performed using the input signal set and are used to generate first and second control signals applied to an output device coupled to the first and second signal processing apparatus to provide complementary control of the output device. - View Dependent Claims (22, 23)
-
Specification