Suppression of diffusion in epitaxial buried plate for deep trenches

• US 8,470,684 B2
• Filed: 05/12/2011
• Issued: 06/25/2013
• Est. Priority Date: 05/12/2011
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Pei, Chengwen, Wang, Geng
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/106,349
• Publication Number:
  US 20120286392A1
• Time in Patent Office: 775 Days
• Field of Search: 438/386, 438/391
• US Class Current: 438/391
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate including a vertical stack, from bottom to top, of at least a semiconductor substrate layer having a doping of a first conductivity type at a first dopant concentration at a lower portion thereof, a first-conductivity-type semiconductor layer having dopants of said first conductivity type at a second dopant concentration greater than said first dopant concentration, and a second-conductivity-type semiconductor layer having a doping of a second conductivity type that is the opposite of said first conductivity type;

at least one deep trench capacitor comprising a node dielectric, an inner electrode, and a portion of said second-conductivity-type semiconductor layer, wherein said node dielectric is vertically spaced from said first-conductivity-type semiconductor layer; and

a deep isolation trench vertically extending through said second-conductivity-type semiconductor layer and at least partly into said first-conductivity-type semiconductor layer.

2. The semiconductor structure of claim 1, wherein said deep isolation trench laterally surrounds said portion of said second-conductivity-type semiconductor layer.

3. The semiconductor structure of claim 2, wherein said portion of said second-conductivity-type semiconductor layer is an outer electrode of said at least one deep trench capacitor.

4. The semiconductor structure of claim 1, wherein said vertical stack further comprises:

a buried insulator layer contacting a top surface of said second-conductivity-type semiconductor layer; and

a top semiconductor layer contacting a top surface of said buried insulator layer.

5. The semiconductor structure of claim 4, further comprising at least one semiconductor device located on said top semiconductor layer.

6. The semiconductor structure of claim 4, further comprising at least one buried contact via structure extending through said top semiconductor layer and said buried insulator layer and contacting said second-conductivity-type semiconductor layer.

7. The semiconductor structure of claim 1, further comprising a dielectric liner contacting an entirety of sidewalls and a bottom surface of said deep isolation trench and having a same composition as said at least one node dielectric.

8. The semiconductor structure of claim 7, further comprising a deep isolation trench fill portion contacting inner sidewalls of said dielectric liner and comprising a conductive material portion having a same composition as said at least one inner electrode.

9. The semiconductor structure of claim 8, wherein said dielectric liner and said conductive material portion completely fills said deep isolation trench.

10. The semiconductor structure of claim 8, wherein said deep isolation trench fill portion further comprises a dielectric material portion embedded within said conductive material portion.

11. The semiconductor structure of claim 1, wherein said second-conductivity-type semiconductor layer has a doping of said second conductivity type at a third dopant concentration that is greater than said second dopant concentration.

12. The semiconductor structure of claim 1, wherein an upper portion of said semiconductor substrate layer has a retrograde dopant concentration profile in which a dopant concentration of first conductivity type dopants decreases from said second dopant concentration to said first dopant concentration.

13. A method of forming a semiconductor structure comprising:

forming a vertical stack, from bottom to top, of at least a semiconductor substrate layer having a doping of a first conductivity type at a first dopant concentration at a lower portion thereof, a first-conductivity-type semiconductor layer having dopants of said first conductivity type at a second dopant concentration greater than said first dopant concentration, and a second-conductivity-type semiconductor layer having a doping of a second conductivity type that is the opposite of said first conductivity type;

forming at least one deep trench capacitor within said vertical stack, wherein each of said at least one deep trench capacitor comprises a node dielectric, an inner electrode, and a portion of said second-conductivity-type semiconductor layer, wherein said node dielectric is vertically spaced from said first-conductivity-type semiconductor layer; and

forming a deep isolation trench vertically extending through said second-conductivity-type semiconductor layer and at least partly into said first-conductivity-type semiconductor layer.

14. The method of claim 13, wherein said deep isolation trench is formed in a pattern that laterally surrounds said portion of said second-conductivity-type semiconductor layer.

15. The method of claim 13, further comprising forming a stack of a buried insulator layer and a top semiconductor layer directly on said second-conductivity-type semiconductor layer, wherein said buried insulator layer contacts a top surface of said second-conductivity-type semiconductor layer.

16. The method of claim 15, further comprising forming at least one buried contact via structure through said top semiconductor layer and said buried insulator layer, wherein said at least one buried contact via structures contacts said second-conductivity-type semiconductor layer.

17. The method of claim 13, wherein said second-conductivity-type semiconductor layer is epitaxially grown on a top surface of said first-conductivity-type semiconductor layer.

18. The method of claim 13, wherein said first-conductivity-type semiconductor layer is formed by implanting dopants of said first conductivity type into an upper portion of said semiconductor substrate layer, wherein said upper portion is converted into said first-conductivity-type semiconductor layer.

19. The method of claim 13, wherein a dielectric liner contacting an entirety of sidewalls and a bottom surface of said deep isolation trench is deposited within said deep isolation trench concurrently with formation of said at least one node dielectric.

20. The method of claim 19, wherein a deep isolation trench fill portion that contacts inner sidewalls of said dielectric liner is deposited within said deep isolation trench concurrently with formation of said at least one inner electrode.