Semiconductor device and method for forming the same

• US 8,470,702 B2
• Filed: 09/14/2012
• Issued: 06/25/2013
• Est. Priority Date: 11/27/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Yang, Hee Jung
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US13/616,584
• Publication Number:
  US 20130005130A1
• Time in Patent Office: 284 Days
• Field of Search: 257/263, 257/E21.447, 257/E29.313, 257/320, 257/328, 257/329, 257/270, 257/271, 257/341, 257/331, 257/332, 257/923, 257/E21.345, 257/E21.629, 257/E29.027, 257/E29.146, 257/E29.262, 438/270, 438/272, 438/589
• US Class Current: 438/589
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a junction region in an upper portion of a semiconductor substrate through an implantation process, wherein the junction region is configured to have a first polarity;

forming a trench defining a buried gate by etching the junction region and the substrate under the junction region;

implanting ions at a sidewall of the trench to form an implantation region, wherein the implantation region is configured to have the first polarity; and

forming a gate electrode within a lower portion of the trench, the gate electrode being formed to overlap with the implantation region.

2. The method of claim 1, wherein the implanting step is performed by a slant ion implantation process.

3. The method of claim 2, wherein the slant ion implantation process has a slant angle of 0.1 degree to 45 degrees.

4. The method of claim 1, wherein forming the ion implantation region comprises performing a plasma ion implantation process.