Method of forming fin structures in integrated circuits

• US 8,470,714 B1
• Filed: 05/22/2012
• Issued: 06/25/2013
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Shih-Hung, Fu, Ssu-I, Lin, Chien-Liang, Chen, Ying-Tsung, Guo, Ted Ming-Lang, Chien, Chin-Cheng, Lin, Chien-Ting, Chiang, Wen-Tai
• Primary Examiner(s): Lee, Jae
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US13/477,079
• Time in Patent Office: 399 Days
• Field of Search: 438/699
• US Class Current: 438/699
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

Claims

1. A method of forming fin structures in integrated circuits, comprising the steps of:

forming a plurality of fin structures on a substrate, wherein a pad layer and a mask layer are formed on the top surface of each said fin structure;

forming an insulating layer on said substrate;

performing a planarization process to remove parts of said insulating layer to expose said mask layer;

performing a wet etching process to etch said insulating layer to expose parts of the sidewalls of said mask layer;

removing said mask layer to expose said pad layer; and

performing a dry etching process to remove said pad layer and parts of said insulating layer to expose the top surface and parts of the sidewalls of said fin structure.

2. A method of forming fin structures in integrated circuits according to claim 1, wherein said wet etching process is performed to etch said insulating layer so that the top surface of said insulating layer is higher than the bottom surface of said mask layer and is lower than the top surface of said mask layer.

3. A method of forming fin structures in integrated circuits according to claim 2, wherein said wet etching process is performed to etch said insulating layer so that the top surface of said insulating layer is at the same level as half of the thickness of said mask layer.

4. A method of forming fin structures in integrated circuits according to claim 1, wherein said wet etching process is a wet etching process using diluted hydrofluoric (DHF) acid.

5. A method of forming fin structures in integrated circuits according to claim 1, wherein said dry etching process is a dry etching process using hydrofluoric (HF) gas and ammonia (NH₃) gas.

6. A method of forming fin structures in integrated circuits according to claim 1, further comprises forming a liner layer on the surface of said fin structure after the step of forming said a plurality of fin structures.

7. A method of forming fin structures in integrated circuits according to claim 1, wherein said mask layer comprises a silicon nitride (SiN) layer.

8. A method of forming fin structures in integrated circuits according to claim 1, wherein said pad layer comprises silicon oxide (SiO₂) layer.

9. A method of forming fin structures in integrated circuits according to claim 1, wherein said insulating layer comprises a silicon oxide (SiO₂) layer.

10. A method of forming fin structures in integrated circuits according to claim 1, wherein the top surface of said exposed fin structure after performing said dry etching process is rounded.