Semiconductor device and method for manufacturing the same

• US 8,471,252 B2
• Filed: 08/05/2009
• Issued: 06/25/2013
• Est. Priority Date: 08/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyairi, Hidekazu, Akimoto, Kengo, Shiraishi, Kojiro
• Primary Examiner(s): Gurley, Lynne
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US12/535,715
• Publication Number:
  US 20100032668A1
• Time in Patent Office: 1,420 Days
• Field of Search: 257/40, 257/43, 257/E21.459, 257/E29.296
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Claims

1. A semiconductor device including a thin film transistor, the thin film transistor comprising:

a first metal oxide layer having n-type conductivity over a source electrode layer;

a second metal oxide layer having n-type conductivity over a drain electrode layer;

an oxide semiconductor layer over the first metal oxide layer and the second metal oxide layer;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the source electrode layer and the drain electrode layer are formed over a substrate,

wherein a carrier concentration of the first metal oxide layer and the second metal oxide layer is higher than a carrier concentration of the oxide semiconductor layer,

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the first metal oxide layer interposed therebetween, and

wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the second metal oxide layer interposed therebetween.

2. The semiconductor device according to claim 1,

wherein an edge of the source electrode layer on the oxide semiconductor layer side is covered with the first metal oxide layer, and

wherein an edge of the drain electrode layer on the oxide semiconductor layer side is covered with the second metal oxide layer.

3. The semiconductor device according to claim 1, wherein each of the first metal oxide layer and the second metal oxide layer contains an impurity element imparting n-type conductivity.

4. The semiconductor device according to claim 1, wherein each of the first metal oxide layer and the second metal oxide layer comprises titanium oxide.

5. The semiconductor device according to claim 1, further comprising:

a first buffer layer between the oxide semiconductor layer and the first metal oxide layer; and

a second buffer layer between the oxide semiconductor layer and the second metal oxide layer,

wherein a carrier concentration of the first buffer layer is higher than the carrier concentration of the oxide semiconductor layer and lower than the carrier concentration of the first metal oxide layer, and

wherein a carrier concentration of the second buffer layer is higher than the carrier concentration of the oxide semiconductor layer and lower than the carrier concentration of the second metal oxide layer.

6. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer each contain titanium.

7. The semiconductor device according to claim 1,

wherein the source electrode layer and the gate electrode layer do not overlap in a region overlapping with a channel formation region of the oxide semiconductor layer, and

wherein the drain electrode layer and the gate electrode layer do not overlap in the region overlapping with the channel formation region of the oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

9. A semiconductor device including a thin film transistor, the thin film transistor comprising:

a first metal oxide layer having n-type conductivity over a source electrode layer;

a second metal oxide layer having n-type conductivity over a drain electrode layer;

an oxide semiconductor layer over the first metal oxide layer and the second metal oxide layer;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein the source electrode layer and the drain electrode layer are formed over a substrate,

wherein each of the first metal oxide layer and the second metal oxide layer extends over the source electrode layer and the drain electrode layer beyond an edge of the oxide semiconductor layer, respectively,

wherein a carrier concentration of the first metal oxide layer and the second metal oxide layer is higher than a carrier concentration of the oxide semiconductor layer,

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the first metal oxide layer interposed therebetween, and

wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the second metal oxide layer interposed therebetween.

10. The semiconductor device according to claim 9,

wherein an edge of the source electrode layer on the oxide semiconductor layer side is covered with the first metal oxide layer, and

wherein an edge of the drain electrode layer on the oxide semiconductor layer side is covered with the second metal oxide layer.

11. The semiconductor device according to claim 9, wherein each of the first metal oxide layer and the second metal oxide layer contains an impurity element imparting n-type conductivity.

12. The semiconductor device according to claim 9, wherein each of the first metal oxide layer and the second metal oxide layer comprises titanium oxide.

13. The semiconductor device according to claim 9, further comprising:

a first buffer layer between the oxide semiconductor layer and the first metal oxide layer; and

a second buffer layer between the oxide semiconductor layer and the second metal oxide layer,

wherein a carrier concentration of the first buffer layer is higher than the carrier concentration of the oxide semiconductor layer and lower than the carrier concentration of the first metal oxide layer, and

wherein a carrier concentration of the second buffer layer is higher than the carrier concentration of the oxide semiconductor layer and lower than the carrier concentration of the second metal oxide layer.

14. The semiconductor device according to claim 9, wherein the source electrode layer and the drain electrode layer each contain titanium.

15. The semiconductor device according to claim 9,

wherein the source electrode layer and the gate electrode layer do not overlap in a region overlapping with a channel formation region of the oxide semiconductor layer, and

wherein the drain electrode layer and the gate electrode layer do not overlap in the region overlapping with the channel formation region of the oxide semiconductor layer.

16. The semiconductor device according to claim 9, wherein the oxide semiconductor layer contains indium, gallium, and zinc.