Information storage system which includes a bonded semiconductor structure

• US 8,471,263 B2
• Filed: 10/19/2009
• Issued: 06/25/2013
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/581,722
• Publication Number:
  US 20100038743A1
• Time in Patent Office: 1,345 Days
• Field of Search: 257/3, 257/74, 257/296, 257/499, 257/618, 257/E27.026, 257/E27.07
• US Class Current: 257/74
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory control device region. The memory device region includes a memory device whose operation is controlled by the vertically oriented memory control device.

Claims

1. A bonded semiconductor structure, comprising:

a vertically oriented semiconductor device carried by a conductive bonding contact region which establishes a bonding interface, the vertically oriented semiconductor device including a mesa structure, and a control dielectric which extends around a sidewall of the mesa structure, the vertically oriented semiconductor device being in communication with an interconnect region through the bonding interface; and

a memory device region in communication with the vertically oriented semiconductor device;

wherein the memory device region is responsive to a signal which flows through the bonding interface.

2. The structure of claim 1, wherein the signal flows through the vertically oriented semiconductor device.

3. The structure of claim 1, wherein the vertically oriented semiconductor device includes a stack of semiconductor regions.

4. The structure of claim 3, wherein the stack extends between the bonding interface and memory device region.

5. The structure of claim 3, wherein the stack includes a planarized surface which faces the bonding interface.

6. The structure of claim 5, wherein the stack includes an opposed planarized surface which faces away from the bonding interface.

7. The structure of claim 1, wherein the memory device region includes a ferroelectric memory device.

8. The structure of claim 1, wherein the memory device region includes phase change memory device.

9. The structure of claim 1, wherein the memory device region includes a magnetoresistive memory device.

10. The structure of claim 1, wherein the signal is adjustable in response to adjusting a signal which flows through the Internet.

11. The structure of claim 1, wherein the signal is adjustable in response to adjusting a signal which flows through a cellular network.

12. A bonded semiconductor structure, comprising:

a vertically oriented semiconductor device in communication with an interconnect region through a bonding interface, wherein the vertically oriented semiconductor device includes a mesa structure;

a memory device region in communication with the vertically oriented semiconductor device;

a conductive bonding contact region which carries the mesa structure; and

a control dielectric which extends around a sidewall of the mesa structure.

13. The structure of claim 12, wherein the mesa structure includes a planarized surface which faces the bonding interface.

14. The structure of claim 12, wherein the memory device region is responsive to a signal which flows through the bonding interface and conductive bonding contact region.

15. The structure of claim 12, further including a control terminal operatively coupled with the mesa structure through the control dielectric.

16. The structure of claim 12, wherein the mesa structure extends between the conductive bonding contact region and memory device region.

17. The structure of claim 12, wherein the memory device region is responsive to a first signal which flows through the bonding interface, the first signal being adjustable in response to adjusting a second signal which flows through the Internet.

18. The structure of claim 12, wherein the memory device region is responsive to a first signal which flows through the bonding interface, the first signal being adjustable in response to adjusting a second signal which flows through a cellular network.