Process-variation tolerant series-connected NMOS and PMOS diodes, and standard cells, tags, and sensors containing the same
First Claim
1. A circuit, comprising:
- a) an NMOS diode having at least one printed or laser-written structure therein;
b) a PMOS diode having at least one printed or laser-written structure therein, the PMOS diode being in series with the NMOS diode between first and second complementary nodes or first and second signal lines of a differential signal path; and
c) a metal wire connecting the NMOS diode to the PMOS diode in series.
3 Assignments
0 Petitions
Accused Products
Abstract
Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
15 Citations
32 Claims
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1. A circuit, comprising:
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a) an NMOS diode having at least one printed or laser-written structure therein; b) a PMOS diode having at least one printed or laser-written structure therein, the PMOS diode being in series with the NMOS diode between first and second complementary nodes or first and second signal lines of a differential signal path; and c) a metal wire connecting the NMOS diode to the PMOS diode in series. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A circuit, comprising:
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a) an NMOS diode having at least one printed or laser-written structure therein configured to receive a first voltage; b) a PMOS diode having at least one printed or laser-written structure therein configured to receive a second voltage different from the first voltage; and c) a metal wire connecting the NMOS diode to the PMOS diode in series, wherein the circuit is configured to provide a relatively stable, constant output voltage between the first and second voltages. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A circuit, comprising:
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a) an NMOS diode comprising a first metal layer and an n-doped semiconductor layer, having at least one structure therein formed from a first liquid phase ink containing a silane and/or silicon nanoparticles; b) a PMOS diode comprising a second metal layer and a p-doped semiconductor layer, having at least one structure therein formed from a second liquid phase ink, the second liquid phase ink being the same as or different from the first liquid phase ink; and c) a metal wire connecting the NMOS diode to the PMOS diode in series. - View Dependent Claims (28, 29, 30, 31, 32)
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Specification