X-Y address type solid state image pickup device and method of producing the same

• US 8,471,317 B2
• Filed: 07/03/2012
• Issued: 06/25/2013
• Est. Priority Date: 07/11/2001
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Ryoji, Mabuchi, Keiji, Mori, Tomonori
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): Belousov, Alexander
• Application Number:
  US13/541,455
• Publication Number:
  US 20120267692A1
• Time in Patent Office: 357 Days
• Field of Search: 257/294, 257/184, 257/187, 257/292, 257/444, 257/E31.058
• US Class Current: 257/294
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/02164 for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer, wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Claims

1. A solid state image pickup device comprising:

a semiconductor layer having a first surface and a light-receiving surface, said light-receiving surface being opposite to said first surface;

a P-type well extending into said semiconductor layer from said first surface, an N-type photo-electric conversion region being between a first portion of the well and a second portion of the well;

a P-type backside layer extending into said semiconductor layer from said light-receiving surface, said photo-electric conversion region being between an N-type region and said backside layer,

wherein said photo-electric conversion region is in physical contact with said N-type region, an N-type conductivity being greater in said N-type region than in said photo-electric conversion region.

2. The device of claim 1, further comprising:

a P-type layer extending into said semiconductor layer from said first surface, said N-type region being between said photo-electric conversion region and said P-type layer.

3. The device of claim 2, wherein said P-type layer is in physical contact with said N-type region.

4. The device of claim 2, further comprising:

a P-type an isolation layer extending into said semiconductor layer from said first surface, said isolation layer being adjacent to said P-type layer and below a gate electrode.

5. The device of claim 4, wherein said gate electrode is in a wiring layer, said wiring layer being over said first surface.

6. The device of claim 1, wherein said first portion is in physical contact with said backside layer.

7. The device of claim 6, wherein said second portion is in physical contact with said backside layer.

8. The device of claim 1, wherein said photo-electric conversion region is in physical contact with said backside layer and said first portion.

9. The device of claim 8, wherein said photo-electric conversion region is in physical contact with said second portion.

10. The device of claim 1, wherein a surface area of the first portion at the first surface is larger than a surface area of the first portion at the backside layer.

11. The device of claim 1, wherein a surface area of the photo-electric conversion region at the backside layer is larger than a surface area of the photo-electric conversion region at the N-type region.

12. The device of claim 1, wherein said backside layer is in a pixel region of the semiconductor layer and a peripheral circuit region of the semiconductor layer, said photo-electric conversion region being in said pixel region.

13. The device of claim 1, further comprising:

a different P-type well within said peripheral circuit region, said different P-type well extending into said semiconductor layer from said first surface.

14. The device of claim 13, wherein an N-type portion of the semiconductor layer is between said backside layer and said different P-type well.

15. The device of claim 13, further comprising:

a light-shielding film covering said peripheral circuit region and said pixel region, an opening through said light-shielding film exposing said light-receiving surface in the pixel region.

16. The device of claim 15, wherein incident light is transmissible through said opening and onto said light-receiving surface.

17. The device of claim 15, further comprising:

an insulating film between said light-shielding film and said light-receiving surface.