Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

• US 8,471,340 B2
• Filed: 11/30/2009
• Issued: 06/25/2013
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Ellis-Monaghan, John J., Joseph, Alvin J., Levy, Max G., Phelps, Richard A., Slinkman, James A., Wolf, Randy L.
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US12/627,343
• Publication Number:
  US 20110127529A1
• Time in Patent Office: 1,303 Days
• Field of Search: 257/369, 257/104, 257/17, 257/192, 257/231, 257/292, 257/32, 257/321, 257/336, 257/361, 257/372, 257/38, 257/514, 438/287, 438/606, 438/288, 438/174, 438/149, 438/151
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Claims

1. A semiconductor structure comprise:

a semiconductor substrate a first surface and a second surface opposite said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a dopant having a given conductivity type such that said first portion has said given conductivity type; and

a second portion extending from said first portion to said second surface, said second portion comprising, in a second concentration greater than said first concentration, any of the following such that said second portion has said given conductivity type;

a same dopant as in said first portion,

a different dopant than in said first portion, said different dopant having said given conductivity type, and

a combination of said same dopant as in said first portion and said different dopant than in said first portion;

an insulator layer on said semiconductor substrate immediately adjacent to said second surface; and

at least one semiconductor device on said insulator layer directly above said first portion and said second portion.

2. The semiconductor structure of claim 1, said first portion having a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion having a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

3. The semiconductor structure of claim 1, said second portion comprising an implant region.

4. The semiconductor structure of claim 1, said semiconductor structure comprising a multi-layer semiconductor structure with said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer.

5. The semiconductor structure of claim 4, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising any of a second silicon layer and a polysilicon layer.

6. The semiconductor structure of claim 1, further comprising a device layer on said insulator layer.

7. The semiconductor structure of claim 1, said second portion suppressing formation of a parasitic inversion charge layer at said second surface and, thereby reducing harmonic behavior.

24. The semiconductor structure of claim 1, said insulator layer comprising an oxide layer.

8. A semiconductor structure comprise:

a semiconductor substrate having a first surface and a second surface opposite said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a dopant having a given conductivity type such that said first portion has said given conductivity type; and

a second portion extending from said first portion to said second surface, said second portion comprising, in a second concentration greater than said first concentration, a same dopant as in said first portion such that said second portion has said given conductivity type;

an insulator layer on said semiconductor substrate immediately adjacent to said second surface; and

,

multiple semiconductor devices on said insulator layer above said first portion and second portion, said second portion suppressing formation of a parasitic inversion charge layer at said second surface so as to reduce harmonic behavior.

9. The semiconductor structure of claim 8, said first portion having a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion having a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

10. The semiconductor structure of claim 8, said second portion comprising an implant region in said semiconductor substrate.

11. The semiconductor structure of claim 8, said semiconductor structure comprising a multi-layer semiconductor structure with said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer, said second semiconductor layer being different from said first semiconductor layer.

12. The semiconductor structure of claim 11, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising a polysilicon layer.

25. The semiconductor structure of claim 8, said insulator layer comprising an oxide layer.

13. A semiconductor structure comprise:

a semiconductor substrate having a first surface and a second surface opposite said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a first dopant having a given conductivity type such that said first portion has said given conductivity type; and

a second portion extending from said first portion to said second surface, said second portion comprising, in a second concentration greater than said first concentration, a second dopant different from said first dopant, said second dopant having said given conductivity type such that said second portion has said given conductivity type;

an insulator layer on said semiconductor substrate immediately adjacent to said second surface; and

,

multiple semiconductor devices on said insulator layer above said first portion and second portion, said second portion suppressing formation of a parasitic inversion charge layer at said second surface so as to reduce harmonic behavior.

14. The semiconductor structure of claim 13, said first portion having a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion having a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

15. The semiconductor structure of claim 13, said second portion comprising an implant region in said semiconductor substrate.

16. The semiconductor structure of claim 13, said semiconductor structure comprising a multi-layer semiconductor structure with said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer, said second semiconductor layer being different from said first semiconductor layer.

17. The semiconductor structure of claim 16, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising a polysilicon layer.

18. A semiconductor structure comprise:

a semiconductor substrate having a first surface and a second surface opposite said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface and comprising, in a first concentration, a first dopant having a given conductivity type such that said first portion has said given conductivity type; and

a second portion extending from said first portion to said second surface, said second portion comprising, in a second concentration greater than said first concentration, a combination of said first dopant and a second dopant different from said first dopant, said second dopant having said given conductivity type such that said second portion has said given conductivity type;

an insulator layer on said semiconductor substrate immediately adjacent to said second surface; and

,

multiple semiconductor devices on said insulator layer above said first portion and second portion, said second portion suppressing formation of a parasitic inversion charge layer at said second surface so as to reduce harmonic behavior.

19. The semiconductor structure of claim 18, said first portion having a resistance of at least 10 ohm-centimeters (Ω

-cm) and said second portion having a sheet resistance of at least 1×

10³ ohms per square (Ω

/□

).

20. The semiconductor structure of claim 18, said second portion comprising an implant region in said semiconductor substrate.

21. The semiconductor structure of claim 18, said semiconductor structure comprising a multi-layer semiconductor structure with said first portion comprising a first semiconductor layer and said second portion comprising a second semiconductor layer on said first semiconductor layer, said second semiconductor layer being different from said first semiconductor layer.

22. The semiconductor structure of claim 21, said first semiconductor layer comprising a silicon layer and said second semiconductor layer comprising a polysilicon layer.

23. A semiconductor structure comprise:

a semiconductor substrate having a first surface and a second surface opposite said first surface, said semiconductor substrate comprising;

a first portion adjacent to said first surface being doped with Boron in a first concentration such that said first portion has a P-type conductivity type; and

a second portion extending from said first portion to said second surface, said second portion being doped with Boron in a second concentration greater than said first concentration such that said second portion has said P-type conductivity type;

an insulator layer on said semiconductor substrate immediately adjacent to said second surface; and

,

multiple semiconductor devices on said insulator layer above said first portion and second portion, said second portion suppressing formation of a parasitic inversion charge layer at said second surface so as to reduce harmonic behavior.