3D inductor and transformer

• US 8,471,358 B2
• Filed: 06/01/2010
• Issued: 06/25/2013
• Est. Priority Date: 06/01/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Kuo, Chin-Wei, Hu, Hsien-Pin, Liu, Sally, Chen, Ming-Fa, Lu, Jhe-Ching
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US12/791,705
• Publication Number:
  US 20110291232A1
• Time in Patent Office: 1,120 Days
• Field of Search: 257/531, 257/E29.325, 438/121
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA

Abstract

In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Claims

1. A semiconductor device comprising:

a semiconductor die comprising a first metallization layer, the first metallization layer comprising a first conductive pattern, the first conductive pattern being in a first dielectric layer;

an interposer comprising a substrate and a second metallization layer on the substrate, the second metallization layer comprising a second conductive pattern, the second conductive pattern being in a second dielectric layer;

first conductive bumps on a first side of the interposer and bonding the semiconductor die to the interposer, some of the first conductive bumps electrically coupling the first conductive pattern to the second conductive pattern to form a coil; and

second conductive bumps on a second side of the interposer, the second side being opposite the first side.

2. The semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern each comprises at least two trace links, wherein the at least two trace links of one of the first conductive pattern and the second conductive pattern extend in multiple directions, each of the at least two trace links coupling a respective adjacent pair of the at least two trace links of the other of the first conductive pattern and the second conductive pattern.

3. The semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern each comprises a ring-shape of conductive materials.

4. The semiconductor device of claim 1, wherein the interposer further comprises a through substrate via penetrating through the substrate, the through substrate via being electrically coupled to the second conductive pattern.

5. The semiconductor device of claim 1, wherein:

the semiconductor die further comprises a third metallization layer, the first metallization layer being on the third metallization layer, wherein the third metallization layer comprises a third conductive pattern, and

the interposer further comprises a fourth metallization layer, the second metallization layer being on the fourth metallization layer, wherein the fourth metallization layer comprises a fourth conductive pattern, wherein the third conductive pattern is electrically coupled to the fourth conductive pattern to form an outer coil surrounding the coil, the coil being an inner coil.

6. The semiconductor device of claim 1 further comprising:

the second metallization layer being on a surface of the substrate opposite the semiconductor die; and

through substrate vias extending through the substrate, the through substrate vias electrically coupling the first conductive pattern to the second conductive pattern.

17. The semiconductor device of claim 1 further comprising a through substrate via extending through the substrate of the interposer, the through substrate via being electrically coupled to at least one of the conductive bumps.

7. A structure comprising:

an interposer comprising;

a substrate;

a first metallization layer on a first side of the substrate, the first metallization layer comprising a first conductive pattern;

a second metallization layer on the first metallization layer, the second metallization layer comprising a second conductive pattern;

a third metallization layer on a second side of the substrate, the second side being opposite the first side, the third metallization layer comprising a third conductive pattern;

a fourth metallization layer on the third metallization layer, the fourth metallization layer comprising a fourth conductive pattern; and

through substrate vias (TSVs) extending through the substrate, wherein at least one TSV electrically couples one of the first conductive pattern and the second conductive pattern to one of the third conductive pattern and the fourth conductive pattern to form a first coil, and at least one other TSV electrically couples one of the first conductive pattern and the second conductive pattern to one of the third conductive pattern and fourth conductive pattern to form a second coil, the first coil being capable of having a first electrical current, the second coil being capable of having a second electrical current at a same time as the first coil has the first electrical current, the first electrical current being distinct from the second electrical current;

a first conductive bump over the first side of the substrate, the first conductive bump being electrically coupled to at least one of the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern; and

a second conductive bump over the second side of the substrate, the second conductive bump being electrically coupled to at least one of the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern.

8. The interposer of claim 7, wherein the first conductive pattern, the second conductive pattern, the third conductive pattern, and the fourth conductive pattern each comprises at least two trace links, wherein the at least two trace links of each of the first conductive pattern and the second conductive pattern extend in at least two directions, wherein the at least one TSV electrically couples the first conductive pattern to the one of the third conductive pattern and the fourth conductive pattern, and wherein the at least one other TSV electrically couples the second conductive pattern to the other of the third conductive pattern and the fourth conductive pattern.

9. The interposer of claim 8, wherein the at least one TSV electrically couples the first conductive pattern to the third conductive pattern, and wherein the at least one other TSV electrically couples the second conductive pattern to the fourth conductive pattern.

10. The interposer of claim 7, wherein the first conductive pattern and the third conductive pattern each comprises a ring-shape, wherein the at least one TSV electrically couples the first conductive pattern to the third conductive pattern, and wherein the at least one other TSV electrically couples the first conductive pattern to the third conductive pattern.

11. The interposer of claim 10, wherein the second conductive pattern and the fourth conductive pattern each comprises a cross link.

12. The interposer of claim 7, wherein the first coil is an inner coil surrounded by the second coil.

13. A method for forming a semiconductor device, the method comprising:

providing a semiconductor die comprising a first substrate and a first dielectric layer over the first substrate, the first dielectric layer having a first conductive pattern in the first dielectric layer;

providing an interposer comprising a second substrate and a second dielectric layer over the second substrate, the second dielectric layer having a second conductive pattern in the second dielectric layer; and

bonding the semiconductor die to the interposer using conductive bumps, wherein at least one of the conductive bumps electrically couples the first conductive pattern to the second conductive pattern to form a coil.

14. The method of claim 13 further comprising forming a through substrate via (TSV) extending through the second substrate, the TSV being electrically coupled to the second conductive pattern.

15. The method of claim 13, wherein the first conductive pattern comprises at least two trace links extending in a first direction, and the second conductive pattern comprises at least two trace links extending in a second direction different from the first direction.

16. The method of claim 13, wherein the first conductive pattern and the second conductive pattern each comprises a ring-shape.