Top layers of metal for high performance IC's

• US 8,471,384 B2
• Filed: 08/21/2007
• Issued: 06/25/2013
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Pham, Long
• Application Number:
  US11/842,153
• Publication Number:
  US 20070284750A1
• Time in Patent Office: 2,135 Days
• Field of Search: 257/758, 257/207, 257/208, 257/211, 257/759, 257/760
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer; and

a second metallization structure over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said integrated circuit chip has a signal path for passing a signal from said first contact point, up through said first opening, over a distance in a direction of a horizontal plane of said second metallization structure, and down through said second opening to said second contact point.

2. The integrated circuit chip of claim 1, wherein said second metallization structure comprises electroplated copper.

3. The integrated circuit chip of claim 1, wherein said second metallization structure comprises aluminum.

4. The integrated circuit chip of claim 1, wherein said second metallization structure comprises nickel.

5. The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point, wherein said second metallization structure is further on said polymer layer.

6. The integrated circuit chip of claim 5, wherein said polymer layer has a thickness between 2 and 30 micrometers.

7. The integrated circuit chip of claim 5, wherein said polymer layer comprises polyimide.

8. The integrated circuit chip of claim 5, wherein said polymer layer comprises benzocyclobutene (BCB).

9. The integrated circuit chip of claim 1, wherein said nitride layer has a thickness between 0.5 and 2 micrometers.

10. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

11. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer; and

a second metallization structure over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said integrated circuit chip has a signal path for passing a signal from said first contact point, up through said first opening, over a distance in a direction of a horizontal plane of said second metallization structure, and down through said second opening to said second contact point, wherein said second metallization structure comprises an electroplated metal.

12. The integrated circuit chip of claim 11, wherein said first metallization structure comprises electroplated copper.

13. The integrated circuit chip of claim 11, wherein said first metallization structure comprises aluminum.

14. The integrated circuit chip of claim 11 further comprising a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point, wherein said second metallization structure is further on said polymer layer.

15. The integrated circuit chip of claim 14, wherein said polymer layer has a thickness between 2 and 30 micrometers.

16. The integrated circuit chip of claim 14, wherein said polymer layer comprises polyimide.

17. The integrated circuit chip of claim 14, wherein said polymer layer comprises benzocyclobutene (BCB).

18. The integrated circuit chip of claim 11, wherein said nitride layer has a thickness between 0.5 and 2 micrometers.

19. The integrated circuit chip of claim 11, wherein said passivation layer further comprises an oxide layer under said nitride layer.

31. The integrated circuit chip of claim 11, wherein said electroplated metal of said second metallization structure comprises electroplated copper.

20. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

a metal trace over said passivation layer;

multiple power or ground pads arranged in an area array in a region of said integrated circuit chip, wherein said area array has at least four rows defined as multiple center rows and at least four columns, wherein no signal pad is arranged in said area array;

multiple first peripheral pads arranged in at least three rows defined as multiple top rows along a first edge of said integrated circuit chip, wherein one of said multiple first peripheral pads is connected to said metal trace, wherein said multiple first peripheral pads in each of said multiple top rows comprise at least six continuously-arranged signal pads, wherein a first pitch between each neighboring two of said at least six continuously-arranged signal pads in one of said multiple top rows is different from a second pitch between neighboring two of said multiple power or ground pads in one of said multiple center rows;

multiple second peripheral pads arranged in at least three rows defined as multiple bottom rows along a second edge of said integrated circuit chip, wherein said second edge is opposite to said first edge, wherein said multiple second peripheral pads in each of said multiple bottom rows comprise at least six continuously-arranged signal pads, wherein said multiple center rows are between said multiple top rows and said multiple bottom rows, wherein a third pitch between each neighboring two of said at least six continuously-arranged signal pads in one of said multiple bottom rows is different from said second pitch; and

multiple metal bumps on said multiple first and second peripheral pads.

21. The integrated circuit chip of claim 20, wherein said metallization structure comprises electroplated copper.

22. The integrated circuit chip of claim 20, wherein said multiple metal bumps comprise multiple solder bumps over said multiple first and second peripheral pads.

23. The integrated circuit chip of claim 20, wherein said nitride layer has a thickness between 0.5 micrometers and 2 micrometers.

24. The integrated circuit chip of claim 20, wherein said passivation layer further comprises an oxide layer under said nitride layer.

25. The integrated circuit chip of claim 20, wherein said area array has at least five rows and at least five columns.

26. The integrated circuit chip of claim 20, wherein said first pitch is smaller than said second pitch.

32. The integrated circuit chip of claim 20, wherein said at least six continuously-arranged signal pads in each of said multiple top rows comprise at least eight continuously-arranged signal pads, and wherein said at least six continuously-arranged signal pads in each of said multiple bottom rows comprise at least eight continuously-arranged signal pads.

27. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer, a second metal layer over said first metal layer, a first metal interconnect, a second metal interconnect and a third metal interconnect between said first and second metal interconnects, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said first opening has a width between 0.5 and 3 micrometers;

a second metallization structure over said separating layer, over said third metal interconnect and on said first and second contact points, wherein said second metallization structure comprises aluminum in said first and second openings and over said separating layer, wherein said first contact point is connected to said second contact point through said second metallization structure; and

a solder bump on said second metallization structure, wherein said solder bump is connected to said first contact point through said second metallization structure, and wherein said solder bump is connected to said second contact point through said second metallization structure.

28. The integrated circuit chip of claim 27 further comprising a polymer layer over said separating layer.

29. The integrated circuit chip of claim 27, wherein said separating layer comprises a nitride layer.

30. The integrated circuit chip of claim 27, wherein said separating layer comprises an oxide layer.

33. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening; and

a second metallization structure over said separating layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said integrated circuit chip has a signal path for passing a signal from said first contact point, up through said first opening, over a distance in a direction of a horizontal plane of said second metallization structure, and down through said second opening to said second contact point, wherein said second metallization structure comprises aluminum.

34. The integrated circuit chip of claim 33, wherein said separating layer comprises a nitride layer.

35. The integrated circuit chip of claim 33, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers.

36. The integrated circuit chip of claim 33 further comprising a polymer layer over said separating layer, wherein said polymer layer has a thickness between 2 and 30 micrometers.

37. The integrated circuit chip of claim 33 further comprising a polymer layer on said separating layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, wherein said second metallization structure is further on a top surface of said polymer layer.