Power MOSFET contact metallization

• US 8,471,390 B2
• Filed: 05/02/2007
• Issued: 06/25/2013
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Wong, Ronald, Qi, Jason, Terrill, Kyle, Chen, Kuo-In
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US11/799,889
• Publication Number:
  US 20070284754A1
• Time in Patent Office: 2,246 Days
• Field of Search: 257/329, 257/331, 257/E29.262, 257/776
• US Class Current: 257/776
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Claims

1. A structure comprising:

an insulator having a second surface, wherein said second surface is in contact with a first surface of a substrate;

an electrical contact coupled to said insulator;

a first barrier layer deposited over and in contact with all surfaces of said insulator except for said second surface, wherein said first barrier layer is also deposited over and in contact with said substrate between said insulator and an adjacent insulator, wherein said first barrier layer is also deposited between and in contact with said electrical contact and said substrate, wherein a substantially even surface is formed by combining a surface of said first barrier layer and a surface of said electrical contact; and

a semiconductor device formed in said substrate adjacent to and underneath said insulator and entirely isolated physically from said electrical contact and from said first barrier layer by said insulator, said semiconductor device electrically coupled to said electrical contact.

2. The structure of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

3. The structure of claim 1 wherein said electrical contact comprises tungsten.

4. The structure of claim 1 further comprising an electrical connector coupled to said electrical contact.

5. The structure of claim 1 wherein said electrical connector comprises aluminum.

6. The structure of claim 1 wherein said electrical contact has a width in the range of approximately 0.35-0.50 microns, said width measured in a direction parallel to said surface of said electrical contact.

7. A structure comprising:

a semiconductor device formed in a substrate that has a first surface;

an insulator having a second surface, wherein said second surface is in contact with said first surface;

a first barrier layer deposited over and in contact with all surfaces of said insulator except for said second surface, wherein said first barrier layer is also deposited over and in contact with said substrate between said insulator and an adjacent insulator, wherein said first barrier layer is also deposited between and in contact with said electrical contact and said substrate, wherein a substantially even surface is formed by combining a surface of said first barrier layer and a surface of said electrical contact;

an electrical contact electrically coupled to said semiconductor device, wherein said electrical contact comprises tungsten;

a second barrier layer deposited over and in contact with said substantially even surface and extending across and above both said insulator and said electrical contact; and

an electrical connector coupled to said electrical contact, wherein said electrical connector comprises aluminum.

8. The structure of claim 7 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

9. The structure of claim 7 wherein said electrical contact has a width in the range of approximately 0.35-0.50 microns, said width measured in a direction parallel to said substrate.

10. The structure of claim 7 wherein said electrical contact is a planar contact that does not extend into said substrate.

11. The structure of claim 7 wherein said electrical contact is a trench contact that extends into said substrate.