Circuit and method for performing arithmetic operations on current signals

• US 8,471,621 B2
• Filed: 04/27/2012
• Issued: 06/25/2013
• Est. Priority Date: 04/28/2011
• Status: Active Grant

• Current Assignee: IDT Europe GmbH (Renesas Electronics Corporation)
• Original Assignee: Zentrum Mikroelektronik Dresden AG (Renesas Electronics Corporation)
• Inventors: Mailand, Marko, Getzlaff, Stefan
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US13/458,118
• Publication Number:
  US 20120293229A1
• Time in Patent Office: 424 Days
• Field of Search: 327/124, 327/355, 327/361
• US Class Current: 327/361
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45

Abstract

A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Claims

1. Circuit comprising an input means configured to selectively receive a current from a plurality of currents;

a first current mirror with mirror ratio m;

a second current mirror;

a third current mirror;

a cross-multiplexer;

a differential capacitive transimpedance amplifier having

a first capacitance and a first switching element connected in parallel to a negative input port and a first output port of the differential capacitive transimpedance amplifier and

a second capacitance and second switching element connected in parallel to a positive input port and a second output port of the differential capacitive transimpedance amplifier;

the input means being connected to an input port of the first current mirror;

an output port of the first current mirror being connected to input ports of the second and third current mirror;

an output port of the second current mirror being connected to a first input port of the cross-multiplexer;

an output port of the third current mirror being connected to a second input port of the cross-multiplexer;

a first output port of the cross-multiplexer being connected to the negative input port of the differential capacitive transimpedance amplifier and a second output port of the cross-multiplexer being connected to the positive input port of the differential capacitive transimpedance amplifier;

the cross-multiplexer being configured

either to establish a first current path between its first input port and its first output port and a second current path between its second input port and its second output port in direct mode

or to establish a first current path between its first input port and its second output port and a second current path between its second input port and its first output port in reverse mode.

2. The circuit according to claim 1, wherein the first capacitance and the second capacitance are tunable devices or digitally programmable capacitance sub-circuits.

3. The circuit according to claim 1, wherein the input means comprises a multiplexer configured to selectively forward a current from a current source out of a plurality of current sources.

4. The circuit according to claim 1, wherein the input means comprises a plurality of light emitting diodes, a switching element configured to selectively drive one light emitting diode out of the plurality of light emitting diodes, and a light sensitive element.

5. The circuit according to claim 1, wherein an analog-to-digital converter is connected to an output port of the differential capacitive transimpedance amplifier.

6. The circuit according to claim 1, wherein the circuit further comprises a first, second, third, fourth, fifth and sixth capacitor and a third and fourth switching element;

the first capacitance comprising the first and second capacitor, one port of the third capacitor being connected to the first and second capacitor and one port of the third capacitor being connected to ground;

the second capacitance comprising the fourth and fifth capacitor, one port of the sixth capacitor being connected to the fourth and fifth capacitor and one port of the sixth capacitor being connected to ground, the third switching element being in parallel to the second capacitor and the fourth switching element being in parallel to the fifth capacitor.

7. Method for performing an arithmetic operation on a circuit according to claim 1, wherein the input means is configured to receive a first current, wherein the cross-multiplexer is configured to operate in direct mode and the first and second switching elements are off so as to integrate a first current flowing into the first and second capacitance;

and wherein

if a second current is to be added to the first current, the input means is configured to receive the second current, the cross-multiplexer is configured to operate in direct mode, and the first and second switching elements are off so as to integrate the second current flowing into the first and second capacitance; and

if a second current is to be subtracted from the first current, the input means is configured to receive the second current, the cross-multiplexer is configured to operate in reverse mode, and the first and second switching elements are off so as to integrate with reverse polarity the second current flowing into the first and second capacitance.

8. Method according to claim 7, wherein an output of the differential capacitive transimpedance amplifier is digitized by an analog-to-digital converter.

9. Method according to claim 7, wherein the first and second switching elements are switched during reset.

10. Method for performing an arithmetic operation on a circuit according to claim 6, wherein

in high gain mode, the third and fourth switching elements are switched during reset so as to allow a capacitive voltage divider including the second (and third capacitor to operate during charge integration;

or

in low gain mode, the third and fourth switching elements are always on so as to short circuit the second and fifth capacitor.