Liquid crystal display device

• US 8,471,793 B2
• Filed: 04/22/2008
• Issued: 06/25/2013
• Est. Priority Date: 04/27/2007
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Irie, Kentaro, Kitayama, Masae, Shimoshikiryoh, Fumikazu, Tsubata, Toshihide, Yamada, Naoshi
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): XAVIER, ANTONIO J
• Application Number:
  US12/451,092
• Publication Number:
  US 20100118012A1
• Time in Patent Office: 1,890 Days
• Field of Search: None
• US Class Current: 345/87
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

In a liquid crystal display device according to one embodiment of the present invention, when the polarities of the source signal voltages do not change over a plurality of horizontal scanning periods, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the j^th row rises before the source signal voltages change to values that correspond to pixels along the j^th row. Next, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the j^th row falls, and then the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the k^th row (j≠k) rises. The polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the j^th row are inverted after the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the k^th row rises.

Claims

1. A liquid crystal display device, comprising:

a plurality of pixels arranged in a matrix pattern of a plurality of rows and a plurality of columns, each pixel including a first sub-pixel and a second sub-pixel capable of exhibiting different brightnesses at least at a certain gray level;

a plurality of source bus lines each associated with pixels along one of the plurality of columns;

a plurality of gate bus lines each associated with pixels along one of the plurality of rows;

a plurality of TFTs each associated with at least one of the first sub-pixel and the second sub-pixel of one of the plurality of pixels; and

a plurality of storage capacitor bus lines each associated at least with one of the first sub-pixel and the second sub-pixel of each pixel along one of the plurality of rows, wherein

each of the first sub-pixel and the second sub-pixel includes a liquid crystal capacitor and a storage capacitor,

a storage capacitor bus line associated with the storage capacitor of the first sub-pixel of one of the plurality of pixels is electrically independent of a storage capacitor bus line associated with the storage capacitor of the second sub-pixel of the pixel;

a source driver configured to supply source signals to the source bus lines so that when polarities of source signal voltages applied to the plurality of source bus lines do not change over a plurality of horizontal scanning periods, an image write pulse of a gate signal supplied to a gate bus line that corresponds to pixels along a j^th row rises before the source signal voltages applied to the plurality of source bus lines change to values that correspond to pixels along the j^th row;

the source driver configured to supply the source signals to the source bus lines so that after the source signal voltages change to values that correspond to pixels along the j^th row, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the j^th row falls, and then the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along a k^th row (j≠

k) to be scanned next rises; and

a control circuit configured to supply storage capacitor signal voltages to the storage capacitor bus lines so that polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the j^th row are inverted after the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the k^th row rises, instead of in synchronism with the rise of the image write pulse of the gate signal supplied to the gate bus line that corresponds to pixels along the k^th row.

2. The liquid crystal display device of claim 1, further comprising:

a gate driver configured to supply gate signals so that an image write pulse of one of the gate signals of a corresponding one of the plurality of gate bus lines rises in synchronism with a fall of a pulse of a gate clock signal, and the image write pulse falls in synchronism with a rise of the next pulse of the gate clock signal.

3. The liquid crystal display device of claim 2, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted in synchronism with a data clock signal having a higher frequency than the gate clock signal.

4. The liquid crystal display device of claim 3, further comprising a counting circuit for counting the number of pulses of the data clock signal,

wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted based on the number of pulses of the data clock signal, which has been counted by the counting circuit since the fall of the next pulse of the gate clock signal.

5. The liquid crystal display device of claim 2, wherein

the source driver is configured to supply the source signals to the source bus lines so that the source signal voltages change in synchronism with a fall of a pulse of a latch strobe signal;

and

a fall of the pulse of the gate clock signal in synchronism with the rise of the image write pulse of the gate signal corresponding to pixels along the j^th row is prior to the fall of the pulse of the latch strobe signal in synchronism with the change of the source signal voltages to values that correspond to pixels along the j^th row.

6. The liquid crystal display device of claim 5, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the j^th row are inverted in synchronism with the fall of the pulse of the latch strobe signal in synchronism with the change of the source signal voltages to values that correspond to pixels along the k^th row.

7. The liquid crystal display device of claim 2, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted in synchronism with a pulse subsequent to the next pulse of the gate clock signal.

8. The liquid crystal display device of claim 1, wherein at least one of the plurality of storage capacitor bus lines is associated with the first sub-pixel of each pixel along a certain one of the plurality of rows and the second sub-pixel of each pixel along another row that is adjacent in a column direction to the certain row.

9. The liquid crystal display device of claim 1, wherein the k^th row is a j+1^th row.

10. The liquid crystal display device of claim 1, wherein the k^th row is a j+2^th row.

11. The liquid crystal display device of claim 10, wherein

the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the storage capacitor signal voltage supplied to each of the plurality of storage capacitor bus lines has such a waveform that the polarity thereof changes at least once within one vertical scanning period;

the vertical scanning period includes a plurality of sub-vertical scanning periods; and

the plurality of sub-vertical scanning periods include,

a first sub-vertical scanning period in which interlaced scanning is performed so that either one of pixels along odd-numbered rows and pixels along even-numbered rows are scanned successively; and

a second sub-vertical scanning period in which interlaced scanning is performed so that the other one of the pixels along odd-numbered rows and the pixels along even-numbered rows are scanned successively after the first sub-vertical scanning period.

12. The liquid crystal display device of claim 11, wherein

the source driver is configured so that the polarity of the source signal voltage supplied to each of plurality of source bus lines changes in a predetermined sequence, wherein the sequence includes two consecutive vertical scanning periods differing from each other in terms of the polarity of the source signal voltage or two consecutive sub-vertical scanning periods differing from each other in terms of the polarity of the source signal voltage;

and

the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that at least one of the storage capacitor signal voltages has such a waveform that an effect of increasing or decreasing an effective voltage of one of two sub-pixels of a pixel connected to a j^th gate bus line selected in the first sub-vertical scanning period that is associated with the storage capacitor bus line to which the storage capacitor signal voltage is supplied is opposite to an effect of increasing or decreasing an effective voltage of one of two sub-pixels of a pixel connected to a j+1^th gate bus line selected in the second sub-vertical scanning period that is associated with the storage capacitor bus line to which the storage capacitor signal voltage is supplied.

13. The liquid crystal display device of claim 12, wherein

the source driver is configured so that the sequence of the source signal voltage includes two consecutive vertical scanning periods differing from each other in terms of the polarity of the source signal voltage, and the first sub-vertical scanning period and the second sub-vertical scanning period, which belong to the same vertical scanning period, are the same in terms of the polarity of the source signal voltage;

and

the control circuit is configured so that the polarity of the storage capacitor signal voltage changes an odd number of times during a period from a point in time when a gate signal voltage supplied to the j^th gate bus line changes from a high level to a low level in the first sub-vertical scanning period until a point in time when a gate signal voltage supplied to the j+1^th gate bus line changes from the high level to the low level in the second sub-vertical scanning period.

14. The liquid crystal display device of claim 12, wherein

the source driver is configured so that the sequence of the source signal voltage includes two consecutive sub-vertical scanning periods differing from each other in terms of the polarity of the source signal voltage, and the first sub-vertical scanning period and the second sub-vertical scanning period, which belong to the same vertical scanning period, differ from each other in terms of the polarity of the source signal voltage;

and

the control circuit is configured so that the polarity of the storage capacitor signal voltage changes an even number of times during a period from a point in time when a gate signal voltage supplied to the j^th gate bus line changes from a high level to a low level in the first sub-vertical scanning period until a point in time when a gate signal voltage supplied to the j+1^th gate bus line changes from the high level to the low level in the second sub-vertical scanning period.

15. A television set, comprising the liquid crystal display device of claim 1.

16. A liquid crystal display device, comprising:

a plurality of pixels arranged in a matrix pattern of a plurality of rows and a plurality of columns, each pixel including a first sub-pixel and a second sub-pixel capable of exhibiting different brightnesses at least at a certain gray level;

a plurality of source bus lines each associated with pixels along one of the plurality of columns;

a plurality of gate bus lines each associated with pixels along one of the plurality of rows;

a plurality of TFTs each associated with at least one of the first sub-pixel and the second sub-pixel of one of the plurality of pixels; and

a plurality of storage capacitor bus lines each associated at least with one of the first sub-pixel and the second sub-pixel of each pixel along one of the plurality of rows, wherein

each of the first sub-pixel and the second sub-pixel includes a liquid crystal capacitor and a storage capacitor;

a storage capacitor bus line associated with the storage capacitor of the first sub-pixel of one of the plurality of pixels is electrically independent of a storage capacitor bus line associated with the storage capacitor of the second sub-pixel of the pixel;

a source driver configured to supply source signals to the source bus lines so that when polarities of source signal voltages applied to the plurality of source bus lines do not change over a plurality of horizontal scanning periods, an image write pulse of a gate signal supplied to a gate bus line that corresponds to pixels along a j^th row rises before the source signal voltages applied to the plurality of source bus lines change to values that correspond to pixels along the j^th row;

the source driver configured to supply the source signals to the source bus lines so that after the source signal voltages change to values that correspond to pixels along the j^th row, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the j^th row falls, and then the source signal voltages change from values that correspond to pixels along the j^th row to values that correspond to pixels along a k^th row (j≠

k); and

a control circuit configured to supply storage capacitor signal voltages to the storage capacitor bus lines so that polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the j^th row are inverted in synchronism with, or subsequent to, a timing at which the source signal voltages start changing from values that correspond to pixels along the j^th row to values that correspond to pixels along the k^th row.

17. The liquid crystal display device of claim 16, further comprising:

a gate driver configured to supply gate signals so that wherein an image write pulse of one of the gate signals of a corresponding one of the plurality of gate bus lines rises in synchronism with a fall of a pulse of a gate clock signal, and the image write pulse falls in synchronism with a rise of the next pulse of the gate clock signal.

18. The liquid crystal display device of claim 17, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted in synchronism with a data clock signal having a higher frequency than the gate clock signal.

19. The liquid crystal display device of claim 18, further comprising a counting circuit for counting the number of pulses of the data clock signal,

wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted based on the number of pulses of the data clock signal, which has been counted by the counting circuit since the fall of the next pulse of the gate clock signal.

20. The liquid crystal display device of claim 17, wherein

the source driver is configured to supply the source signals to the source bus lines so that the source signal voltages change in synchronism with a fall of a pulse of a latch strobe signal;

and

a fall of the pulse of the gate clock signal in synchronism with the rise of the image write pulse of the gate signal corresponding to pixels along the j^th row is prior to the fall of the pulse of the latch strobe signal in synchronism with the change of the source signal voltages to values that correspond to pixels along the j^th row.

21. The liquid crystal display device of claim 20, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the j^th row are inverted in synchronism with the fall of the pulse of the latch strobe signal in synchronism with the change of the source signal voltages to values that correspond to pixels along the k^th row.

22. The liquid crystal display device of claim 17, wherein the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the polarities of the storage capacitor signal voltages are inverted in synchronism with a pulse subsequent to the next pulse of the gate clock signal.

23. The liquid crystal display device of claim 16, wherein at least one of the plurality of storage capacitor bus lines is associated with the first sub-pixel of each pixel along a certain one of the plurality of rows and the second sub-pixel of each pixel along another row that is adjacent in a column direction to the certain row.

24. The liquid crystal display device of claim 16, wherein the k^th row is a j+1^th row.

25. The liquid crystal display device of claim 16, wherein the k^th row is a j+2^th row.

26. The liquid crystal display device of claim 25, wherein

the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that the storage capacitor signal voltage supplied to each of the plurality of storage capacitor bus lines has such a waveform that the polarity thereof changes at least once within one vertical scanning period;

the vertical scanning period includes a plurality of sub-vertical scanning periods; and

the plurality of sub-vertical scanning periods includes;

a first sub-vertical scanning period in which interlaced scanning is performed so that either one of pixels along odd-numbered rows and pixels along even-numbered rows are scanned successively; and

a second sub-vertical scanning period in which interlaced scanning is performed so that the other one of the pixels along odd-numbered rows and the pixels along even-numbered rows are scanned successively after the first sub-vertical scanning period.

27. The liquid crystal display device of claim 26, wherein

the source driver is configured so that the polarity of the source signal voltage supplied to each of the plurality of source bus lines changes in a predetermined sequence, wherein the sequence includes two consecutive vertical scanning periods differing from each other in terms of the polarity of the source signal voltage or two consecutive sub-vertical scanning periods differing from each other in terms of the polarity of the source signal voltage;

and

the control circuit is configured to supply the storage capacitor signal voltages to the storage capacitor bus lines so that at least one of the storage capacitor signal voltages has such a waveform that an effect of increasing or decreasing an effective voltage of one of two sub-pixels of a pixel connected to a j^th gate bus line selected in the first sub-vertical scanning period that is associated with the storage capacitor bus line to which the storage capacitor signal voltage is supplied is opposite to an effect of increasing or decreasing an effective voltage of one of two sub-pixels of a pixel connected to a j+1^th gate bus line selected in the second sub-vertical scanning period that is associated with the storage capacitor bus line to which the storage capacitor signal voltage is supplied.

28. The liquid crystal display device of claim 27, wherein

the source driver is configured so that the sequence of the source signal voltage includes two consecutive vertical scanning periods differing from each other in terms of the polarity of the source signal voltage, and the first sub-vertical scanning period and the second sub-vertical scanning period, which belong to the same vertical scanning period, are the same in terms of the polarity of the source signal voltage;

and

the control circuit is configured so that the polarity of the storage capacitor signal voltage changes an odd number of times during a period from a point in time when a gate signal voltage supplied to the j^th gate bus line changes from a high level to a low level in the first sub-vertical scanning period until a point in time when a gate signal voltage supplied to the j+1^th gate bus line changes from the high level to the low level in the second sub-vertical scanning period.

29. The liquid crystal display device of claim 27, wherein

the source driver is configured so that the sequence of the source signal voltage includes two consecutive sub-vertical scanning periods differing from each other in terms of the polarity of the source signal voltage, and the first sub-vertical scanning period and the second sub-vertical scanning period, which belong to the same vertical scanning period, differ from each other in terms of the polarity of the source signal voltage;

and

the control circuit is configured so that the polarity of the storage capacitor signal voltage changes an even number of times during a period from a point in time when a gate signal voltage supplied to the j^th gate bus line changes from a high level to a low level in the first sub-vertical scanning period until a point in time when a gate signal voltage supplied to the j+1^th gate bus line changes from the high level to the low level in the second sub-vertical scanning period.