Signal control circuit and method thereof, liquid crystal display and timing controller thereof

• US 8,471,839 B2
• Filed: 07/08/2008
• Issued: 06/25/2013
• Est. Priority Date: 09/17/2007
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Lin, Hao-Shun
• Primary Examiner(s): Awad, Amr
• Assistant Examiner(s): WILLIS, RANDAL L
• Application Number:
  US12/168,924
• Publication Number:
  US 20090073157A1
• Time in Patent Office: 1,813 Days
• Field of Search: 345/211, 345/212
• US Class Current: 345/212
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/027 Arrangements or methods related to powering off a display
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A signal control circuit and a method thereof, and a liquid crystal display (LCD) and a timing controller thereof are provided. The signal control circuit of the present invention maintains a voltage level of a driving signal output from the timing controller for driving data drivers to the supply voltage, such that the data drivers may cease outputting display data to the liquid crystal display panel when the LCD is turned off. Therefore, the image sticking, ghost image and fan-out phenomenon occurred when the LCD is turned off may be avoided.

Claims

1. A signal control circuit, suitable for a liquid crystal display (LCD), the signal control circuit comprising:

a bus, for transmitting a low voltage differential signal (LVDS) clock supplied to a timing controller of the LCD; and

a control unit, comprising a transistor having a source, a drain and a gate, wherein the source is electrically connected to a reference level, the gate is used for receiving the LVDS clock, and the drain is electrically connected to a high level supply voltage,

wherein the control unit is configured to detect a voltage level of a common-mode voltage of the LVDS clock,

wherein when the control unit detects that the voltage level of the common-mode voltage of the LVDS clock drops to the reference level, a voltage level of a driving signal, which is output from the timing controller and required for driving a plurality of data drivers of the LCD by the timing controller, is maintained by the control unit to the high level supply voltage and then the driving signal with the high level supply voltage is supplied to the plurality of data drivers of the LCD, such that output from the data drivers is stopped outputting to an LCD panel of the LCD,

wherein residual charges within pixel array of the LCD panel are quickly dissipated in response to the stopped output of the data drivers.

2. The signal control circuit as claimed in claim 1, wherein the control unit further comprises:

a unity gain amplifier, having an input connected to the drain of the transistor; and

a diode, having an anode connected to an output of the unity gain amplifier, and a cathode coupled to the driving signal.

3. The signal control circuit as claimed in claim 2, wherein the unity gain amplifier comprises a positive input terminal served as the input of the unity gain amplifier, a negative input terminal and an output terminal served as the output of the unity gain amplifier, wherein the positive input terminal is electrically connected to the drain, and the negative input terminal and the output terminal are electrically connected to one another to couple to the driving signal.

4. The signal control circuit as claimed in claim 3, wherein the anode is electrically connected to the output terminal, and the cathode is coupled to the driving signal.

5. The signal control circuit as claimed in claim 1, wherein the control unit further comprises:

a first resistor, electrically connected between the high level supply voltage and the drain; and

a second resistor, electrically connected between the reference level and the gate.

6. The signal control circuit as claimed in claim 1, wherein the reference level comprises a ground level.

7. A signal control method, suitable for a liquid crystal display (LCD), the signal control method comprising:

detecting a voltage level of a common-mode voltage of an LVDS clock supplied to a timing controller of the LCD; and

maintaining a voltage level of a driving signal, which is output from the timing controller and required for driving a plurality of data drivers of the LCD by the timing controller, to a high level supply voltage when the voltage level of the common-mode voltage drops to a reference level, such that the driving signal with the high level supply voltage is supplied to the data drivers, and output from the data drivers is stopped outputting to an LCD panel of the LCD,

wherein residual charges within pixel array of the LCD panel are quickly dissipated in response to the stopped output of the data drivers.

8. The signal control method as claimed in claim 7, wherein the step of detecting of the voltage level of the common-mode voltage comprises:

receiving the LVDS clock through a gate of a transistor, wherein a source of the transistor is electrically connected to the reference level, and a drain of the transistor is electrically connected to the high level supply voltage and is coupled to the driving signal through a series-connected unity gain amplifier and diode; and

deciding the voltage level of the common-mode voltage based on whether or not the transistor is turned on,

wherein when the transistor is turned off, the voltage level of the common-mode voltage is the reference level.

9. The signal control method as claimed in claim 7, wherein the reference level comprises a ground level.

10. A liquid crystal display (LCD), comprising:

an LCD panel;

a plurality of data drivers; and

a signal control circuit, for detecting a voltage level of a common-mode voltage of an LVDS clock supplied to a timing controller of the LCD, so as to maintain a voltage level of a driving signal, which is output from the timing controller and required for driving the plurality of data drivers of the LCD by the timing controller, to a high level supply voltage when the voltage level of the common-mode voltage drops to a reference level,

wherein the plurality of data drivers are electrically connected to the signal control circuit and the LCD panel, wherein output from the data drivers is stopped outputting to the LCD panel in response to the driving signal maintained to the high level supply voltage when the voltage level of the common-mode voltage drops to the reference level,

wherein residual charges within pixel array of the LCD panel are quickly dissipated in response to the stopped output of the data drivers.

11. The LCD as claimed in claim 10 further comprising a plurality of scan drivers electrically connected to the LCD panel, wherein each of the scan drivers provide a scan signal according to a basic timing to sequentially activate a corresponding row of pixels, such that the row of pixels may correspondingly receive the display data output from each of the data drivers.

12. The LCD as claimed in claim 11, wherein the signal control circuit comprises:

a bus, for transmitting the LVDS clock; and

a control unit, comprising a transistor having a source, a drain and a gate, wherein the source is electrically connected to the reference level, the gate is used for receiving the LVDS clock, and the drain is electrically connected to the high level supply voltage.

13. The LCD as claimed in claim 12, wherein the control unit further comprises:

a unity gain amplifier, having an input connected to the drain of the transistor; and

a diode, having an anode connected to an output of the unity gain amplifier, and a cathode coupled to the driving signal.

14. The LCD as claimed in claim 13, wherein the unity gain amplifier comprises a positive input terminal served as the input of the unity gain amplifier, a negative input terminal and an output terminal served as the output of the unity gain amplifier, wherein the positive input terminal is electrically connected to the drain, and the negative input terminal and the output terminal are electrically connected to one another to couple to the driving signal.

15. The LCD as claimed in claim 13, wherein the anode is electrically connected to the output terminal, and the cathode is coupled to the driving signal.

16. The LCD as claimed in claim 12, wherein the control unit further comprises:

a first resistor, electrically connected between the high level supply voltage and the drain; and

a second resistor, electrically connected between the reference level and the gate.

17. The LCD as claimed in claim 12, wherein the timing controller is electrically connected to the signal control circuit, and configured for receiving and processing the LVDS clock and an LVDS data transmitted from the bus to individually provide a required clock signal, an image signal and the driving signal to each of the data drivers, and provide the required basic timing to each of the scan drivers.

18. The LCD as claimed in claim 12, further comprising a power supply unit for providing the high level supply voltage, the reference level and power required for operating the LCD.

19. The LCD as claimed in claim 10, wherein the reference level comprises a ground level.

20. A timing controller, suitable for a liquid crystal display (LCD), the timing controller characterized by:

at least one flip-flop, for controlling a voltage level of a driving signal, which is output from the timing controller and required for driving a plurality of data drivers by the timing controller, to be maintained to a high level supply voltage when a voltage level of a common-mode voltage of an LVDS clock received by the timing controller drops to a reference level by a detection of the flip-flop, wherein the reference level comprises a ground level, and the high level supply voltage comprises a high level voltage,

wherein output from the data drivers is stopped outputting to an LCD panel of the LCD in response to the driving signal maintained to the supply voltage,

wherein residual charges within pixel array of the LCD panel are quickly dissipated in response to the stopped output of the data drivers.

21. The timing controller as claimed in claim 20, wherein the flip-flop comprises a D flip-flop, a T flip-flop, an RS flip-flop or a JK flip-flop.

22. A liquid crystal display (LCD), comprising:

a plurality of data drivers, each of the data drivers receiving a corresponding driving signal, an image signal and a clock signal;

a timing controller, electrically connected to the data drivers and comprising at least one flip-flop, wherein the timing controller is used for receiving and processing an LVDS clock and an LVDS data transmitted from a bus to individually provide the clock signal, the image signal and the driving signal to the corresponding data drivers; and

an LCD panel, electrically connected to the data drivers, for correspondingly receiving a display data output from each of the data drivers to display an image,

wherein when a voltage level of a common-mode voltage of the LVDS clock received by the timing controller drops to a reference level by a detection of the flip-flop, a voltage level of the driving signal, which is output from the timing controller and required for driving the plurality of data drivers by the timing controller, is maintained to a high level supply voltage under control of the flip-flop, and output from the data drivers is stopped outputting to the LCD panel in response to the driving signal maintained to the high level supply voltage, such that residual charges within pixel array of the LCD panel is quickly dissipated in response to the stopped output of the data drivers.

23. The LCD as claimed in claim 22 further comprising a plurality of scan drivers electrically connected to the LCD panel, and each of the scan drivers providing a scan signal according to a basic timing to sequentially activate a corresponding row of pixels, such that the row of pixels may correspondingly receive the display data output from each of the data drivers, wherein the basic timing is generated from the LVDS clock after being processed by the timing controller.

24. The LCD as claimed in claim 22, further comprising a power supply unit for providing the high level supply voltage, the reference level and power required for operating the LCD.

25. The LCD as claimed in claim 22, wherein the flip-flop comprises a D flip-flop, a T flip-flop, an RS flip-flop or a JK flip-flop.