Grid-tie inverter for interconnecting AC voltage to electric power grid

• US 8,472,215 B2
• Filed: 07/12/2012
• Issued: 06/25/2013
• Est. Priority Date: 01/13/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mochikawa, Hiroshi, Koyama, Yushi, Tsuda, Junichi
• Primary Examiner(s): Vu, Bao Q
• Application Number:
  US13/547,552
• Publication Number:
  US 20120275201A1
• Time in Patent Office: 348 Days
• Field of Search: 363/39, 363/40, 363/41, 363/131, 363/132
• US Class Current: 363/40
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/123 Suppression of common mode voltage or current
• CPC Class Codes: H02M 1/126 using passive filters
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.

Claims

1. A grid-tie inverter comprising:

a single-phase or three-phase inverter that performs pulse width modulation for a DC voltage supplied from a DC power supply;

a first capacitor circuit connected to an input side of the inverter so as to form a neutral point;

a second capacitor circuit connected to an output side of the inverter so as to form a neutral point;

a common mode current bypass channel formed by connecting the neutral point of the first capacitor circuit and the neutral point of the second capacitor circuit to each other;

a grounded capacitor provided between the bypass channel and a ground;

a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit, the first common mode choke coil unit that suppresses a common mode current occurring in the inverter;

an output filter converting a pulse width-modulated voltage waveform outputted from the inverter into a sine single-phase or three-phase AC voltage, the output filter positioned between the inverter and the second capacitor circuit; and

a grid transformer connected to an output side of the second capacitor circuit, a neutral point of the grid transformer connected to the ground through a neutral ground line, wherein

at a switching frequency of the inverter, an impedance of the bypass channel is smaller than an impedance of a leakage current channel formed in which a leakage current flows through such a route that goes from the neutral point of the grid transformer to a stray capacitance of the DC power supply through the ground.

2. The grid-tie inverter according to claim 1, further comprising:

a second common mode choke coil unit including a common mode choke coil at least one of on a DC power supply side of the first capacitor circuit and on a grid side of the second capacitor circuit, the second common mode choke coil unit that suppresses propagation of a common mode noise.

3. The grid-tie inverter according to claim 1, further comprising:

a first resistor provided between the grounded capacitor and the ground, the first resistor that suppresses a resonance.

4. The grid-tie inverter according to claim 1, further comprising:

a second resistor provided on a way of the bypass channel, the second resistor that controls the resonance.

5. The grid-tie inverter according to claim 1, further comprising:

a reactor arranged between the output filter and the second capacitor circuit, the reactor composing an LC filter together with a capacitor composing the output filter or with the second capacitor circuit, the LC filter suppressing a normal mode harmonic noise.

6. The grid-tie inverter according to claim 2, wherein

the second common mode choke coil unit includes the common mode choke coil at least on the grid side of the second capacitor circuit, and

a capacitor arranged on a grid side of the common mode choke coil provided on the grid side of the second capacitor circuit composes an LC filter that suppresses a normal mode harmonic noise together with an inductance component of the common mode choke coil provided on the grid side of the second capacitor circuit.

8. The grid-tie inverter according to claim 1, further comprising:

a booster circuit including a first switching element, the booster circuit boosting a DC voltage supplied from a DC power supply;

a second switching element provided in the inverter, the inverter performing three-level pulse width modulation for an output of the booster circuit; and

a control circuit that creates a gate control signal controlling ON/OFF switching of the first switching element provided in the booster circuit and the second switching element provided in the inverter, wherein

based on a carrier with a predetermined frequency and on a waveform in which a phase of the carrier is adjusted, the control unit creates the gate control signal for controlling variations of a neutral point potential that occurs following the switching of the first switching element provided in the booster circuit and variations of a neutral point potential that occurs following the switching of the second switching element provided in the inverter so that frequencies and phases of both of the variations can coincide with each other.

7. A grid-tie inverter comprising:

a single-phase or three-phase inverter that performs pulse width modulation for a DC voltage supplied from a DC power supply;

a first capacitor circuit connected to an input side of the inverter;

a second capacitor circuit connected to an output side of the inverter;

a common mode current bypass channel formed by connecting one end of the first capacitor circuit and one end of the second capacitor circuit to each other, or connecting the one end of the first capacitor circuit and a neutral point of the second capacitor circuit, or connecting a neutral point of the first capacitor circuit and the one end of the second capacitor circuit;

a capacitor provided in the bypass channel;

a grounded capacitor provided between the bypass channel and a ground;

a first common mode choke coil unit including a common mode choke coil at least one between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit, the first common mode choke coil unit that suppresses a common mode current occurring in the inverter;

an output filter converting a pulse width-modulated voltage waveform outputted from the inverter into a sine single-phase or three-phase AC voltage, the output filter positioned between the inverter and the second capacitor circuit; and

a grid transformer connected to an output side of the second capacitor circuit, a neutral point of the grid transformer connected to the ground through a neutral ground line, wherein

at a switching frequency of the inverter, an impedance of the bypass channel is smaller than an impedance of a leakage current channel formed in which a leakage current flows through such a route that goes from the neutral point of the grid transformer to a stray capacitance of the DC power supply through the ground.

9. A grid-tie inverter comprising;

a single-phase or three-phase inverter that performs pulse width modulation for a DC voltage supplied from a DC power supply;

a first capacitor circuit connected to an input side of the inverter so as to form a neutral point;

a second capacitor circuit connected to an output side of the inverter so as to form a neutral point;

a common mode current bypass channel formed by connecting the neutral point of the first capacitor circuit and the neutral point of the second capacitor circuit to each other;

a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit, the first common mode choke coil unit that suppresses a common mode current occurring in the inverter;

an output filter converting a pulse width-modulated voltage waveform outputted from the inverter into a sine single-phase or three-phase AC voltage, the output filter composed of first reactors and a first capacitor, the output filter positioned between the inverter and the second capacitor circuit;

a resonance suppression circuit that suppresses a resonance occurring between inter-winding capacitance of the common mode choke coil and the first reactor of the output filter; and

a grid transformer connected to an output side of the second capacitor circuit, a neutral point of the grid transformer connected to the ground through a neutral ground line, wherein

at a switching frequency of the inverter, an impedance of the bypass channel is smaller than an impedance of a leakage current channel formed in which a leakage current flows through such a route that goes from the neutral point of the grid transformer to a stray capacitance of the DC power supply through the ground.

10. The grid-tie inverter according to claim 9, wherein

the resonance suppression circuit includes resistors each connected in parallel to respective-phase first reactors of the output filter.

11. The grid-tie inverter according to claim 9, wherein

the resonance suppression circuit includes series circuits each composed of a resistor and a second capacitor, each of the series circuits connected in parallel to respective-phase first reactors of the output filter.

12. The grid-tie inverter according to claim 9, further comprising:

a resistor connected in parallel to a winding of the common mode choke coil.

13. The grid-tie inverter according to claim 9, wherein

the resonance suppression circuit includes a series circuit composed of a resistor and a second capacitor, the series circuit connected in parallel to windings of the common mode choke coil.

14. The grid-tie inverter according to claim 9, wherein

the resonance suppression circuit includes windings connected in series to routes of components connected in parallel to respective-phase first reactors of the output filter, and

the resonance suppression circuit is composed in a manner that the winding of one phase and the winding of the other one phase are magnetically coupled to each other so as to have low impedance for a common mode and to have high impedance for a normal mode.

15. The grid-tie inverter according to claim 9, wherein

the resonance suppression circuit includes a resistor in the common mode current bypass channel.

16. The grid-tie inverter according to claim 15, wherein

the resonance suppression circuit includes a second reactor connected in parallel to the resistor provided in the common mode current bypass channel.