Semiconductor memory device

• US 8,472,231 B2
• Filed: 03/31/2011
• Issued: 06/25/2013
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/076,787
• Publication Number:
  US 20110249484A1
• Time in Patent Office: 817 Days
• Field of Search: 365/51, 365/63, 365/65, 365/145, 365/149
• US Class Current: 365/63
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An object is to provide a semiconductor memory device which stores data with the use of a transistor having small leakage current between a source and a drain in an off state as a writing transistor. In a matrix including a plurality of memory cells, gates of the writing transistors are connected to writing word lines. In each of the memory cells, a drain of the writing transistor is connected to a gate of a reading transistor, and the drain is connected to one electrode of a capacitor. Further, the other electrode of the capacitor is connected to a reading word line. In the semiconductor memory device in which the memory cells are connected in series so as to have a NAND structure, gates of the reading transistors are provided alternately, and the reading word line and the writing word line are shared.

Claims

1. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising;

a first memory cell;

a second memory cell;

a third memory cell; and

a fourth memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring are orthogonal to each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein the third memory cell comprises a fifth transistor, a sixth transistor, and a third capacitor,

wherein the fourth memory cell comprises a seventh transistor, an eighth transistor, and a fourth capacitor,

wherein a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a drain of the fifth transistor is electrically connected to a gate of the sixth transistor and one electrode of the third capacitor,

wherein a drain of the seventh transistor is electrically connected to a gate of the eighth transistor and one electrode of the fourth capacitor,

wherein a gate of the fifth transistor is electrically connected to the first wiring,

wherein a gate of the first transistor and the other electrode of the third capacitor are electrically connected to the second wiring,

wherein the other electrode of the first capacitor and a gate of the seventh transistor are electrically connected to the third wiring,

wherein a gate of the third transistor and the other electrode of the fourth capacitor are electrically connected to the fourth wiring,

wherein the drain of the first transistor is electrically connected to a source of the third transistor,

wherein a drain of the second transistor is electrically connected to a source of the fourth transistor,

wherein the drain of the fifth transistor is electrically connected to a source of the seventh transistor,

wherein a drain of the sixth transistor is electrically connected to a source of the eighth transistor,

wherein the first transistor, the third transistor, the fifth transistor, and the seventh transistor have the same conductivity type,

wherein the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor have the same conductivity type, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

2. The semiconductor memory device according to claim 1, wherein the conductivity type of the second transistor is p-type.

3. The semiconductor memory device according to claim 1, further comprising a ninth transistor,

wherein a source of the first transistor is electrically connected to a drain of the ninth transistor,

wherein a source of the ninth transistor is electrically connected to the fifth wiring, and

wherein a gate of the ninth transistor is electrically connected to the first wiring.

4. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising;

a first memory cell;

a second memory cell;

a third memory cell; and

a fourth memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring are orthogonal to each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein the third memory cell comprises a fifth transistor, a sixth transistor, and a third capacitor,

wherein the fourth memory cell comprises a seventh transistor, an eighth transistor, and a fourth capacitor,

wherein a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a drain of the fifth transistor is electrically connected to a gate of the sixth transistor and one electrode of the third capacitor,

wherein a drain of the seventh transistor is electrically connected to a gate of the eighth transistor and one electrode of the fourth capacitor,

wherein a gate of the first transistor and the other electrode of the third capacitor are electrically connected to the first wiring,

wherein the other electrode of the first capacitor and a gate of the seventh transistor are electrically connected to the second wiring,

wherein a gate of the third transistor and the other electrode of the fourth capacitor are electrically connected to the third wiring,

wherein the other electrode of the second capacitor is electrically connected to the fourth wiring,

wherein the drain of the first transistor is electrically connected to a source of the third transistor,

wherein a drain of the second transistor is electrically connected to a source of the fourth transistor,

wherein the drain of the fifth transistor is electrically connected to a source of the seventh transistor,

wherein a drain of the sixth transistor is electrically connected to a source of the eighth transistor, and

wherein the first to eighth transistors have the same conductivity type.

5. The semiconductor memory device according to claim 4, wherein the conductivity type of the second transistor is n-type.

6. The semiconductor memory device according to claim 4, further comprising a ninth transistor, a tenth transistor, and a sixth wiring,

wherein a drain of the fourth transistor is electrically connected to a source of the ninth transistor,

wherein a drain of the eighth transistor is electrically connected to a source of the tenth transistor,

wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to the sixth wiring, and

wherein the sixth wiring is parallel to the first wiring.